Merge tag 'phy-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...

Kishon writes:

phy: for 4.3

*) Add new NXP USB OTG PHY driver
*) Add vbus/id detection, extcon support and fixes in phy-sun4i-usb
   driver
*) Add support to use phy-sun4i-usb driver for sun8i-a23 and sun8i-a33
   SoCs
*) Other trivial code cleanups, dropping .owner assignment and constify
   phy_ops

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --cc drivers/phy/Kconfig
index 6b8dd162f644214ba24fd666b5aa6c94467d964d,0fe9bff7b37b4e83f805fde4b95302f1685444c2..47da573d0babd8bb9805c8cdb9a9d40323567bf8
--- 1/drivers/phy/Kconfig
--- 2/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@@ -54,9 -54,19 +54,20 @@@ config PHY_EXYNOS_MIPI_VIDE
          Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
          and EXYNOS SoCs.
  
+ config PHY_LPC18XX_USB_OTG
+       tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
+       depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
+       depends on MFD_SYSCON
+       select GENERIC_PHY
+       help
+         Enable this to support NXP LPC18xx/43xx internal USB OTG PHY.
+ 
+         This driver is need for USB0 support on LPC18xx/43xx and takes
+         care of enabling and clock setup.
+ 
  config PHY_PXA_28NM_HSIC
        tristate "Marvell USB HSIC 28nm PHY Driver"
 +      depends on HAS_IOMEM
        select GENERIC_PHY
        help
          Enable this to support Marvell USB HSIC PHY driver for Marvell

diff --cc drivers/phy/phy-berlin-usb.c
Simple merge

diff --cc drivers/phy/phy-sun4i-usb.c
index 2dad7e820ff0b16b7447b708f0c147b2e0289f02,623c7143152e432f15fac0a5e7d209b0b28adc15..731b395d6e6a1621ee7fc36055b6c1a5f7367780
--- 1/drivers/phy/phy-sun4i-usb.c
--- 2/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@@ -212,9 -372,8 +372,9 @@@ void sun4i_usb_phy_set_squelch_detect(s
  
        sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
  }
 +EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
  
- static struct phy_ops sun4i_usb_phy_ops = {
+ static const struct phy_ops sun4i_usb_phy_ops = {
        .init           = sun4i_usb_phy_init,
        .exit           = sun4i_usb_phy_exit,
        .power_on       = sun4i_usb_phy_power_on,

diff --cc drivers/phy/phy-ti-pipe3.c
index 08020dc2c7c8c3496987589841fc0ddb0b1c9ff7,2038f1945f2c133cae52dad762f2f34b4412a821..93bc1120af12844ca17cd53e7869dba0676b438b
--- 1/drivers/phy/phy-ti-pipe3.c
--- 2/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@@ -256,49 -250,36 +256,49 @@@ static int ti_pipe3_exit(struct phy *x
        u32 val;
        unsigned long timeout;
  
 -      /* SATA DPLL can't be powered down due to Errata i783 and PCIe
 -       * does not have internal DPLL
 +      /* If dpll_reset_syscon is not present we wont power down SATA DPLL
 +       * due to Errata i783
         */
 -      if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
 -          of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
 +      if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
 +          !phy->dpll_reset_syscon)
                return 0;
  
 -      /* Put DPLL in IDLE mode */
 -      val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 -      val |= PLL_IDLE;
 -      ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 +      /* PCIe doesn't have internal DPLL */
 +      if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 +              /* Put DPLL in IDLE mode */
 +              val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 +              val |= PLL_IDLE;
 +              ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  
 -      /* wait for LDO and Oscillator to power down */
 -      timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 -      do {
 -              cpu_relax();
 -              val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 -              if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 -                      break;
 -      } while (!time_after(jiffies, timeout));
 +              /* wait for LDO and Oscillator to power down */
 +              timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 +              do {
 +                      cpu_relax();
 +                      val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 +                      if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 +                              break;
 +              } while (!time_after(jiffies, timeout));
 +
 +              if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 +                      dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 +                              val);
 +                      return -EBUSY;
 +              }
 +      }
  
 -      if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 -              dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 -                      val);
 -              return -EBUSY;
 +      /* i783: SATA needs control bit toggle after PLL unlock */
 +      if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
 +              regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 +                                 SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
 +              regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 +                                 SATA_PLL_SOFT_RESET, 0);
        }
  
 +      ti_pipe3_disable_clocks(phy);
 +
        return 0;
  }
- static struct phy_ops ops = {
+ static const struct phy_ops ops = {
        .init           = ti_pipe3_init,
        .exit           = ti_pipe3_exit,
        .power_on       = ti_pipe3_power_on,