drm/amdkfd: hard-code MALL cacheline size for gfx11, gfx12

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Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: David Belanger <david.belanger@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index d73510c522868f64b964c6f1f22dc9fcdccc72bf..e5324c5bc6c71454178b6a9a97a57cd5c12ebd4e 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1504,7 +1504,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
                                        CRAT_CACHE_FLAGS_DATA_CACHE |
                                        CRAT_CACHE_FLAGS_SIMD_CACHE);
                pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
-               pcache_info[i].cache_line_size = 0;
+               pcache_info[i].cache_line_size = 64;
                i++;
        }
        return i;