}
        }
 
+       /* AMD chipsets often cause the communication stalls upon certain
+        * sequence like the pin-detection.  It seems that forcing the synced
+        * access works around the stall.  Grrr...
+        */
+       if (chip->pci->vendor == PCI_VENDOR_ID_AMD ||
+           chip->pci->vendor == PCI_VENDOR_ID_ATI) {
+               snd_printk(KERN_INFO SFX "Enable sync_write for AMD chipset\n");
+               chip->bus->sync_write = 1;
+               chip->bus->allow_bus_reset = 1;
+       }
+
        /* Then create codec instances */
        for (c = 0; c < max_slots; c++) {
                if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
 
        spec->multiout.dac_nids = spec->dac_nids;
        spec->init = stac92hd83xxx_core_init;
 
-       if (codec->bus->pci && codec->bus->pci->vendor == PCI_VENDOR_ID_AMD) {
-               snd_printk(KERN_INFO "idt92hd83xxx: "
-                          "Enable sync_write for AMD chipset\n");
-               codec->bus->sync_write = 1;
-               codec->bus->allow_bus_reset = 1;
-       }
-
        spec->board_config = snd_hda_check_board_config(codec,
                                                        STAC_92HD83XXX_MODELS,
                                                        stac92hd83xxx_models,
        if (get_wcaps(codec, 0xa) & AC_WCAP_IN_AMP)
                snd_hda_sequence_write_cache(codec, unmute_init);
 
-       /* Some HP machines seem to have unstable codec communications
-        * especially with ATI fglrx driver.  For recovering from the
-        * CORB/RIRB stall, allow the BUS reset and keep always sync
-        */
-       if (spec->board_config == STAC_HP_DV5) {
-               codec->bus->sync_write = 1;
-               codec->bus->allow_bus_reset = 1;
-       }
-
        spec->aloopback_ctl = stac92hd71bxx_loopback;
        spec->aloopback_mask = 0x50;
        spec->aloopback_shift = 0;