bool
        default y
        select ARCH_CLOCKSOURCE_DATA
+       select ARCH_HAS_DEBUG_VIRTUAL
        select ARCH_HAS_DEVMEM_IS_ALLOWED
        select ARCH_HAS_ELF_RANDOMIZE
 +      select ARCH_HAS_SET_MEMORY
 +      select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
 +      select ARCH_HAS_STRICT_MODULE_RWX if MMU
        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
        select ARCH_HAVE_CUSTOM_GPIO_H
        select ARCH_HAS_GCOV_PROFILE_ALL
 
  
        /* ensure at least INFORM0 has the resume address */
        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
-               pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
+               pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
  
 -      tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
 -      tmp &= ~EXYNOS5_USE_RETENTION;
 -      pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
 +      tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
 +      tmp &= ~EXYNOS_L2_USE_RETENTION;
 +      pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
  
        tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
        tmp |= EXYNOS5420_UFS;
 
  
  static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
  {
 -      wakeup_secondary();
 +      /*
 +       * write the address of secondary startup into the backup ram register
 +       * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
 +       * backup ram register at offset 0x1FF0, which is what boot rom code
 +       * is waiting for. This will wake up the secondary core from WFE.
 +       */
-       writel(virt_to_phys(secondary_startup),
++      writel(__pa_symbol(secondary_startup),
 +             backupram + UX500_CPU1_JUMPADDR_OFFSET);
 +      writel(0xA1FEED01,
 +             backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
 +
 +      /* make sure write buffer is drained */
 +      mb();
        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
        return 0;
  }