drm/vc4: hvs: Set AXI panic modes

[ Upstream commit df993fced230daa8452892406f3180c93ebf7e7b ]

The HVS can change AXI request mode based on how full the COB
FIFOs are.
Until now the vc4 driver has been relying on the firmware to
have set these to sensible values.

With HVS channel 2 now being used for live video, change the
panic mode for all channels to be explicitly set by the driver,
and the same for all channels.

Fixes: c54619b0bfb3 ("drm/vc4: Add support for the BCM2711 HVS5")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-2-1f8e0770798b@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 4ac9f5a2d5f991287aaf5634b0a226291cc290c5..ee55520c2f11d878bec485bb2bddd94a53ab9943 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -884,6 +884,17 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
                      SCALER_DISPCTRL_DSPEISLUR(2) |
                      SCALER_DISPCTRL_SCLEIRQ);
 
+       /* Set AXI panic mode.
+        * VC4 panics when < 2 lines in FIFO.
+        * VC5 panics when less than 1 line in the FIFO.
+        */
+       dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
+                     SCALER_DISPCTRL_PANIC1_MASK |
+                     SCALER_DISPCTRL_PANIC2_MASK);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
+
        HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 
        ret = devm_request_irq(dev, platform_get_irq(pdev, 0),

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index f0290fad991de2c958433c62189804b6c507c7e9..f121905c404d19579bb096a9ba9f5d16afaa523b 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -220,6 +220,12 @@
 #define SCALER_DISPCTRL                         0x00000000
 /* Global register for clock gating the HVS */
 # define SCALER_DISPCTRL_ENABLE                        BIT(31)
+# define SCALER_DISPCTRL_PANIC0_MASK           VC4_MASK(25, 24)
+# define SCALER_DISPCTRL_PANIC0_SHIFT          24
+# define SCALER_DISPCTRL_PANIC1_MASK           VC4_MASK(27, 26)
+# define SCALER_DISPCTRL_PANIC1_SHIFT          26
+# define SCALER_DISPCTRL_PANIC2_MASK           VC4_MASK(29, 28)
+# define SCALER_DISPCTRL_PANIC2_SHIFT          28
 # define SCALER_DISPCTRL_DSP3_MUX_MASK         VC4_MASK(19, 18)
 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT                18