pinctrl: samsung: Add ARTPEC-8 SoC specific configuration

Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl.

Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Signed-off-by: Priyadarsini G <priya.ganesh@samsung.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Link: https://lore.kernel.org/r/20250901051926.59970-3-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 5fe7c4b9f7bd424f396082f1b1b16bfb65f26cdf..323487dfa8c2cb04067e30d373a577d3197d67d3 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off  = {
        .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
 };
 
+/*
+ * Bank type for non-alive type. Bit fields:
+ * CON: 4, DAT: 1, PUD: 4, DRV: 4
+ */
+static const struct samsung_pin_bank_type artpec_bank_type_off = {
+       .fld_width = { 4, 1, 4, 4, },
+       .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
+};
+
 /* Pad retention control code for accessing PMU regmap */
 static atomic_t exynos_shared_retention_refcnt;
 
@@ -1816,3 +1825,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
        .ctrl           = gs101_pin_ctrl,
        .num_ctrl       = ARRAY_SIZE(gs101_pin_ctrl),
 };
+
+/* pin banks of artpec8 pin-controller (FSYS0) */
+static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = {
+       ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00),
+       ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04),
+       ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08),
+       ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c),
+       ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10),
+       ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14),
+       ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18),
+       ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c),
+       ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20),
+       ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24),
+};
+
+/* pin banks of artpec8 pin-controller (PERIC) */
+static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = {
+       ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+       ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
+       ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+       ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c),
+};
+
+static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = {
+       {
+               /* pin-controller instance 0 FSYS data */
+               .pin_banks      = artpec8_pin_banks0,
+               .nr_banks       = ARRAY_SIZE(artpec8_pin_banks0),
+               .eint_gpio_init = exynos_eint_gpio_init,
+       }, {
+               /* pin-controller instance 1 PERIC data */
+               .pin_banks      = artpec8_pin_banks1,
+               .nr_banks       = ARRAY_SIZE(artpec8_pin_banks1),
+               .eint_gpio_init = exynos_eint_gpio_init,
+       },
+};
+
+const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
+       .ctrl           = artpec8_pin_ctrl,
+       .num_ctrl       = ARRAY_SIZE(artpec8_pin_ctrl),
+};

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 362dc533186fb4ab9926b38b8d34af07690f783d..c9c38f8988dd2c715ffedd6a31e66fdb6712ae6f 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -236,6 +236,16 @@
                .name                   = id                            \
        }
 
+#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs)                     \
+       {                                                               \
+               .type                   = &artpec_bank_type_off,        \
+               .pctl_offset            = reg,                          \
+               .nr_pins                = pins,                         \
+               .eint_type              = EINT_TYPE_GPIO,               \
+               .eint_offset            = offs,                         \
+               .name                   = id                            \
+       }
+
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.

diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 24745e1d78cec59c932ed57fdb8ca85410376ff7..c099195fc464e3d8da7ff4c1ab5e46ef62470fb3 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1482,6 +1482,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
                .data = &s5pv210_of_data },
 #endif
 #ifdef CONFIG_PINCTRL_EXYNOS_ARM64
+       { .compatible = "axis,artpec8-pinctrl",
+               .data = &artpec8_of_data },
        { .compatible = "google,gs101-pinctrl",
                .data = &gs101_of_data },
        { .compatible = "samsung,exynos2200-pinctrl",

diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 1cabcbe1401a614ea33803132db776e97c1d56ee..be2dee886d81a942ed876a9e81142e83ec979679 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -381,6 +381,7 @@ struct samsung_pmx_func {
 };
 
 /* list of all exported SoC specific data */
+extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;