a->ref == b->ref;
 }
 
+static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
+                                  const struct intel_cdclk_config *a,
+                                  const struct intel_cdclk_config *b)
+{
+       /*
+        * FIXME should store a bit more state in intel_cdclk_config
+        * to differentiate squasher vs. cd2x divider properly. For
+        * the moment all platforms with squasher use a fixed cd2x
+        * divider.
+        */
+       if (!has_cdclk_squasher(dev_priv))
+               return false;
+
+       return a->cdclk != b->cdclk &&
+               a->vco != 0 &&
+               a->vco == b->vco &&
+               a->ref == b->ref;
+}
+
 /**
  * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
  *                             configurations requires a modeset on all pipes
        if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
                return false;
 
+       /*
+        * FIXME should store a bit more state in intel_cdclk_config
+        * to differentiate squasher vs. cd2x divider properly. For
+        * the moment all platforms with squasher use a fixed cd2x
+        * divider.
+        */
+       if (has_cdclk_squasher(dev_priv))
+               return false;
+
        return a->cdclk != b->cdclk &&
+               a->vco != 0 &&
                a->vco == b->vco &&
                a->ref == b->ref;
 }
                        pipe = INVALID_PIPE;
        }
 
-       if (intel_cdclk_can_crawl(dev_priv,
-                                 &old_cdclk_state->actual,
-                                 &new_cdclk_state->actual)) {
+       if (intel_cdclk_can_squash(dev_priv,
+                                  &old_cdclk_state->actual,
+                                  &new_cdclk_state->actual)) {
+               drm_dbg_kms(&dev_priv->drm,
+                           "Can change cdclk via squasher\n");
+       } else if (intel_cdclk_can_crawl(dev_priv,
+                                        &old_cdclk_state->actual,
+                                        &new_cdclk_state->actual)) {
                drm_dbg_kms(&dev_priv->drm,
                            "Can change cdclk via crawl\n");
        } else if (pipe != INVALID_PIPE) {