struct regmap *syscon_pol;
        u32 syscon_pol_offset;
+
+       /* DISPC_CONTROL & DISPC_CONFIG lock*/
+       spinlock_t control_lock;
 } dispc;
 
 enum omap_color_component {
 static void mgr_fld_write(enum omap_channel channel,
                                        enum mgr_reg_fields regfld, int val) {
        const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
+       const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
+       unsigned long flags;
+
+       if (need_lock)
+               spin_lock_irqsave(&dispc.control_lock, flags);
+
        REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
+
+       if (need_lock)
+               spin_unlock_irqrestore(&dispc.control_lock, flags);
 }
 
 #define SR(reg) \
 
        dispc.pdev = pdev;
 
+       spin_lock_init(&dispc.control_lock);
+
        r = dispc_init_features(dispc.pdev);
        if (r)
                return r;