extern u32 qib_cpulist_count;
 extern unsigned long *qib_cpulist;
 
-extern unsigned qib_wc_pat;
 extern unsigned qib_cc_table_size;
 int qib_init(struct qib_devdata *, int);
 int init_chip_wc_pat(struct qib_devdata *dd, u32);
 
        vma->vm_flags &= ~VM_MAYREAD;
        vma->vm_flags |= VM_DONTCOPY | VM_DONTEXPAND;
 
-       if (qib_wc_pat)
+       /* We used PAT if wc_cookie == 0 */
+       if (!dd->wc_cookie)
                vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 
        ret = io_remap_pfn_range(vma, vma->vm_start, phys >> PAGE_SHIFT,
 
        qib_6120_config_ctxts(dd);
        qib_set_ctxtcnt(dd);
 
-       if (qib_wc_pat) {
-               ret = init_chip_wc_pat(dd, 0);
-               if (ret)
-                       goto bail;
-       }
+       ret = init_chip_wc_pat(dd, 0);
+       if (ret)
+               goto bail;
        set_6120_baseaddrs(dd); /* set chip access pointers now */
 
        ret = 0;
 
        qib_7220_config_ctxts(dd);
        qib_set_ctxtcnt(dd);  /* needed for PAT setup */
 
-       if (qib_wc_pat) {
-               ret = init_chip_wc_pat(dd, 0);
-               if (ret)
-                       goto bail;
-       }
+       ret = init_chip_wc_pat(dd, 0);
+       if (ret)
+               goto bail;
        set_7220_baseaddrs(dd); /* set chip access pointers now */
 
        ret = 0;
 
        unsigned features, pidx, sbufcnt;
        int ret, mtu;
        u32 sbufs, updthresh;
+       resource_size_t vl15off;
 
        /* pport structs are contiguous, allocated after devdata */
        ppd = (struct qib_pportdata *)(dd + 1);
        qib_7322_config_ctxts(dd);
        qib_set_ctxtcnt(dd);
 
-       if (qib_wc_pat) {
-               resource_size_t vl15off;
-               /*
-                * We do not set WC on the VL15 buffers to avoid
-                * a rare problem with unaligned writes from
-                * interrupt-flushed store buffers, so we need
-                * to map those separately here.  We can't solve
-                * this for the rarely used mtrr case.
-                */
-               ret = init_chip_wc_pat(dd, 0);
-               if (ret)
-                       goto bail;
+       /*
+        * We do not set WC on the VL15 buffers to avoid
+        * a rare problem with unaligned writes from
+        * interrupt-flushed store buffers, so we need
+        * to map those separately here.  We can't solve
+        * this for the rarely used mtrr case.
+        */
+       ret = init_chip_wc_pat(dd, 0);
+       if (ret)
+               goto bail;
 
-               /* vl15 buffers start just after the 4k buffers */
-               vl15off = dd->physaddr + (dd->piobufbase >> 32) +
-                       dd->piobcnt4k * dd->align4k;
-               dd->piovl15base = ioremap_nocache(vl15off,
-                                                 NUM_VL15_BUFS * dd->align4k);
-               if (!dd->piovl15base) {
-                       ret = -ENOMEM;
-                       goto bail;
-               }
+       /* vl15 buffers start just after the 4k buffers */
+       vl15off = dd->physaddr + (dd->piobufbase >> 32) +
+                 dd->piobcnt4k * dd->align4k;
+       dd->piovl15base = ioremap_nocache(vl15off,
+                                         NUM_VL15_BUFS * dd->align4k);
+       if (!dd->piovl15base) {
+               ret = -ENOMEM;
+               goto bail;
        }
+
        qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
 
        ret = 0;
 
 unsigned qib_cc_table_size;
 module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO);
 MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984");
-/*
- * qib_wc_pat parameter:
- *      0 is WC via MTRR
- *      1 is WC via PAT
- *      If PAT initialization fails, code reverts back to MTRR
- */
-unsigned qib_wc_pat = 1; /* default (1) is to use PAT, not MTRR */
-module_param_named(wc_pat, qib_wc_pat, uint, S_IRUGO);
-MODULE_PARM_DESC(wc_pat, "enable write-combining via PAT mechanism");
 
 static void verify_interrupt(unsigned long);
 
                spin_unlock(&dd->pport[pidx].cc_shadow_lock);
        }
 
-       if (!qib_wc_pat)
-               qib_disable_wc(dd);
+       qib_disable_wc(dd);
 
        if (dd->pioavailregs_dma) {
                dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
                goto bail;
        }
 
-       if (!qib_wc_pat) {
-               ret = qib_enable_wc(dd);
-               if (ret) {
-                       qib_dev_err(dd,
-                               "Write combining not enabled (err %d): performance may be poor\n",
-                               -ret);
-                       ret = 0;
-               }
+       ret = qib_enable_wc(dd);
+       if (ret) {
+               qib_dev_err(dd,
+                       "Write combining not enabled (err %d): performance may be poor\n",
+                       -ret);
+               ret = 0;
        }
 
        qib_verify_pioperf(dd);
 
        }
 
        if (!ret) {
-               int cookie;
-
-               cookie = mtrr_add(pioaddr, piolen, MTRR_TYPE_WRCOMB, 1);
-               if (cookie < 0) {
-                       {
-                               qib_devinfo(dd->pcidev,
-                                        "mtrr_add()  WC for PIO bufs failed (%d)\n",
-                                        cookie);
-                               ret = -EINVAL;
-                       }
-               } else {
-                       dd->wc_cookie = cookie;
-                       dd->wc_base = (unsigned long) pioaddr;
-                       dd->wc_len = (unsigned long) piolen;
-               }
+               dd->wc_cookie = arch_phys_wc_add(pioaddr, piolen);
+               if (dd->wc_cookie < 0)
+                       ret = -EINVAL;
        }
 
        return ret;
  */
 void qib_disable_wc(struct qib_devdata *dd)
 {
-       if (dd->wc_cookie) {
-               int r;
-
-               r = mtrr_del(dd->wc_cookie, dd->wc_base,
-                            dd->wc_len);
-               if (r < 0)
-                       qib_devinfo(dd->pcidev,
-                                "mtrr_del(%lx, %lx, %lx) failed: %d\n",
-                                dd->wc_cookie, dd->wc_base,
-                                dd->wc_len, r);
-               dd->wc_cookie = 0; /* even on failure */
-       }
+       arch_phys_wc_del(dd->wc_cookie);
 }
 
 /**