qed: Configure cacheline size in HW

Orabug: 25933053, 26439680

Default HW configuration is optimal for an architecture where cache
line size is 64B.

During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Brian Maly <brian.maly@oracle.com>

diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c
index 44e98591e9407bcbcf5b7c25122eb630de2145c4..c79c2e2446d9a0a20d9b7f24239b06a0ca52db48 100644 (file)
--- a/drivers/net/ethernet/qlogic/qed/qed_dev.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c
@@ -1167,6 +1167,57 @@ static void qed_init_cau_rt_data(struct qed_dev *cdev)
        }
 }
 
+static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
+                                    struct qed_ptt *p_ptt)
+{
+       u32 val, wr_mbs, cache_line_size;
+
+       val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
+       switch (val) {
+       case 0:
+               wr_mbs = 128;
+               break;
+       case 1:
+               wr_mbs = 256;
+               break;
+       case 2:
+               wr_mbs = 512;
+               break;
+       default:
+               DP_INFO(p_hwfn,
+                       "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
+                       val);
+               return;
+       }
+
+       cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
+       switch (cache_line_size) {
+       case 32:
+               val = 0;
+               break;
+       case 64:
+               val = 1;
+               break;
+       case 128:
+               val = 2;
+               break;
+       case 256:
+               val = 3;
+               break;
+       default:
+               DP_INFO(p_hwfn,
+                       "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
+                       cache_line_size);
+       }
+
+       if (L1_CACHE_BYTES > wr_mbs)
+               DP_INFO(p_hwfn,
+                       "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
+                       L1_CACHE_BYTES, wr_mbs);
+
+       STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
+}
+
 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
                              struct qed_ptt *p_ptt, int hw_mode)
 {
@@ -1215,6 +1266,8 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
        qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
        qed_port_unpretend(p_hwfn, p_ptt);
 
+       qed_init_cache_line_size(p_hwfn, p_ptt);
+
        rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
        if (rc)
                return rc;

diff --git a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
index 6d4ac7e2ee83eb50ffb2ec8517a2f2f0992dc2f5..e65397360ab42ceae14130a6c1be80c7e31b243f 100644 (file)
--- a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
@@ -1551,6 +1551,7 @@
 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL
 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL
 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL
+#define PSWRQ2_REG_WR_MBS0 0x240400UL
 
 #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL
 #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL