u32 len = op->data.nbytes;
        int ret;
 
-       if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) {
-               ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
+       if (unlikely(op->max_freq != sfc->frequency)) {
+               ret = clk_set_rate(sfc->clk, op->max_freq);
                if (ret)
                        return ret;
-               sfc->frequency = mem->spi->max_speed_hz;
+               sfc->frequency = op->max_freq;
                dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n",
                        sfc->frequency, clk_get_rate(sfc->clk));
        }
        .adjust_op_size = rockchip_sfc_adjust_op_size,
 };
 
+static const struct spi_controller_mem_caps rockchip_sfc_mem_caps = {
+       .per_op_freq = true,
+};
+
 static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
 {
        struct rockchip_sfc *sfc = dev_id;
 
        host->flags = SPI_CONTROLLER_HALF_DUPLEX;
        host->mem_ops = &rockchip_sfc_mem_ops;
+       host->mem_caps = &rockchip_sfc_mem_caps;
        host->dev.of_node = pdev->dev.of_node;
        host->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;
        host->max_speed_hz = SFC_MAX_SPEED;