drm/amd/display: Do DIO FIFO enable after DP video stream enable

[Why]
Avoids a race condition where DIO FIFO can underflow due to no incoming
data available.

[How]
Shift the FIFO enable below stream enable.

Make sure fullness level is written before the DIO reset takes place
and that we're not doing it twice.

Reviewed-by: Syed Hassan <Syed.Hassan@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
index 914c5da737ed22257a4a17807ab4629a6d75ad78..5d4be1141c4e3739c80543a1deb8d0e57df00ad3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
@@ -56,7 +56,8 @@ static void enc314_enable_fifo(struct stream_encoder *enc)
 
        /* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */
        REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
-       REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1, DIG_FIFO_READ_START_LEVEL, 0x7);
+       REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
+       REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
        REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
        REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
        REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
@@ -316,15 +317,11 @@ static void enc314_stream_encoder_dp_unblank(
        /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
         * that it overflows during mode transition, and sometimes doesn't recover.
         */
-       REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
        REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
        udelay(10);
 
        REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 
-       /* DIG Resync FIFO now needs to be explicitly enabled. */
-       enc314_enable_fifo(enc);
-
        /* wait 100us for DIG/DP logic to prime
         * (i.e. a few video lines)
         */
@@ -340,6 +337,12 @@ static void enc314_stream_encoder_dp_unblank(
 
        REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
 
+       /*
+        * DIG Resync FIFO now needs to be explicitly enabled.
+        * This should come after DP_VID_STREAM_ENABLE per HW docs.
+        */
+       enc314_enable_fifo(enc);
+
        dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
 }