dmaengine: IOATDMA: Cleanup pre v3.0 chansts register reads

Remove pre-3.0 channel status reads. 3.0 and later chansts register
is 64bit and can be read 64bit. This was clarified with the hardware
architects and since the driver now only support 3.0+ we don't need the
legacy support

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 8f4e607d5817be1a84ca50f3cc50564e237ecc36..b8f48074789f2a4907d5c0a219846e067552b9cf 100644 (file)
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -235,43 +235,11 @@ ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
        return ioat_dma->idx[index];
 }
 
-static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan)
-{
-       u8 ver = ioat_chan->ioat_dma->version;
-       u64 status;
-       u32 status_lo;
-
-       /* We need to read the low address first as this causes the
-        * chipset to latch the upper bits for the subsequent read
-        */
-       status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
-       status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
-       status <<= 32;
-       status |= status_lo;
-
-       return status;
-}
-
-#if BITS_PER_LONG == 64
-
 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
 {
-       u8 ver = ioat_chan->ioat_dma->version;
-       u64 status;
-
-        /* With IOAT v3.3 the status register is 64bit.  */
-       if (ver >= IOAT_VER_3_3)
-               status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
-       else
-               status = ioat_chansts_32(ioat_chan);
-
-       return status;
+       return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
 }
 
-#else
-#define ioat_chansts ioat_chansts_32
-#endif
-
 static inline u64 ioat_chansts_to_addr(u64 status)
 {
        return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;

diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
index 909352f74c89237835c3ba306595b47f5cbceab3..4994a3623aee43fb09d88d62314cc9c2cb2472c4 100644 (file)
--- a/drivers/dma/ioat/registers.h
+++ b/drivers/dma/ioat/registers.h
@@ -99,19 +99,9 @@
 #define IOAT_DMA_COMP_V1                       0x0001  /* Compatibility with DMA version 1 */
 #define IOAT_DMA_COMP_V2                       0x0002  /* Compatibility with DMA version 2 */
 
-
-#define IOAT1_CHANSTS_OFFSET           0x04    /* 64-bit Channel Status Register */
-#define IOAT2_CHANSTS_OFFSET           0x08    /* 64-bit Channel Status Register */
-#define IOAT_CHANSTS_OFFSET(ver)               ((ver) < IOAT_VER_2_0 \
-                                               ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
-#define IOAT1_CHANSTS_OFFSET_LOW       0x04
-#define IOAT2_CHANSTS_OFFSET_LOW       0x08
-#define IOAT_CHANSTS_OFFSET_LOW(ver)           ((ver) < IOAT_VER_2_0 \
-                                               ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
-#define IOAT1_CHANSTS_OFFSET_HIGH      0x08
-#define IOAT2_CHANSTS_OFFSET_HIGH      0x0C
-#define IOAT_CHANSTS_OFFSET_HIGH(ver)          ((ver) < IOAT_VER_2_0 \
-                                               ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
+/* IOAT1 define left for i7300_idle driver to not fail compiling */
+#define IOAT1_CHANSTS_OFFSET           0x04
+#define IOAT_CHANSTS_OFFSET            0x08    /* 64-bit Channel Status Register */
 #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL)
 #define IOAT_CHANSTS_SOFT_ERR                  0x10ULL
 #define IOAT_CHANSTS_UNAFFILIATED_ERR          0x8ULL