KVM: arm64: nv: Convert masks to denylists in limit_nv_id_reg()

Consistently use denylisting of features such that the limitations of
KVM's nested implementation are explicitly documented (rather than
implied).

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 77db81bae86f9b1b4f34d63069a3bdebf03190ef..53c57d105c935023c0b82e4762d25a853380d145 100644 (file)
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -1462,9 +1462,18 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
 
        case SYS_ID_AA64PFR1_EL1:
                /* Only support BTI, SSBS, CSV2_frac */
-               val &= (ID_AA64PFR1_EL1_BT      |
-                       ID_AA64PFR1_EL1_SSBS    |
-                       ID_AA64PFR1_EL1_CSV2_frac);
+               val &= ~(ID_AA64PFR1_EL1_PFAR           |
+                        ID_AA64PFR1_EL1_DF2            |
+                        ID_AA64PFR1_EL1_MTEX           |
+                        ID_AA64PFR1_EL1_THE            |
+                        ID_AA64PFR1_EL1_GCS            |
+                        ID_AA64PFR1_EL1_MTE_frac       |
+                        ID_AA64PFR1_EL1_NMI            |
+                        ID_AA64PFR1_EL1_SME            |
+                        ID_AA64PFR1_EL1_RES0           |
+                        ID_AA64PFR1_EL1_MPAM_frac      |
+                        ID_AA64PFR1_EL1_RAS_frac       |
+                        ID_AA64PFR1_EL1_MTE);
                break;
 
        case SYS_ID_AA64MMFR0_EL1:
@@ -1517,12 +1526,16 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
                break;
 
        case SYS_ID_AA64MMFR1_EL1:
-               val &= (ID_AA64MMFR1_EL1_HCX    |
-                       ID_AA64MMFR1_EL1_PAN    |
-                       ID_AA64MMFR1_EL1_LO     |
-                       ID_AA64MMFR1_EL1_HPDS   |
-                       ID_AA64MMFR1_EL1_VH     |
-                       ID_AA64MMFR1_EL1_VMIDBits);
+               val &= ~(ID_AA64MMFR1_EL1_ECBHB         |
+                        ID_AA64MMFR1_EL1_CMOW          |
+                        ID_AA64MMFR1_EL1_TIDCP1        |
+                        ID_AA64MMFR1_EL1_nTLBPA        |
+                        ID_AA64MMFR1_EL1_AFP           |
+                        ID_AA64MMFR1_EL1_ETS           |
+                        ID_AA64MMFR1_EL1_TWED          |
+                        ID_AA64MMFR1_EL1_XNX           |
+                        ID_AA64MMFR1_EL1_SpecSEI       |
+                        ID_AA64MMFR1_EL1_HAFDBS);
                /* FEAT_E2H0 implies no VHE */
                if (test_bit(KVM_ARM_VCPU_HAS_EL2_E2H0, kvm->arch.vcpu_features))
                        val &= ~ID_AA64MMFR1_EL1_VH;
@@ -1564,11 +1577,17 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
 
        case SYS_ID_AA64DFR0_EL1:
                /* Only limited support for PMU, Debug, BPs, WPs, and HPMN0 */
-               val &= (ID_AA64DFR0_EL1_PMUVer  |
-                       ID_AA64DFR0_EL1_WRPs    |
-                       ID_AA64DFR0_EL1_BRPs    |
-                       ID_AA64DFR0_EL1_DebugVer|
-                       ID_AA64DFR0_EL1_HPMN0);
+               val &= ~(ID_AA64DFR0_EL1_ExtTrcBuff     |
+                        ID_AA64DFR0_EL1_BRBE           |
+                        ID_AA64DFR0_EL1_MTPMU          |
+                        ID_AA64DFR0_EL1_TraceBuffer    |
+                        ID_AA64DFR0_EL1_TraceFilt      |
+                        ID_AA64DFR0_EL1_DoubleLock     |
+                        ID_AA64DFR0_EL1_PMSVer         |
+                        ID_AA64DFR0_EL1_CTX_CMPs       |
+                        ID_AA64DFR0_EL1_SEBEP          |
+                        ID_AA64DFR0_EL1_PMSS           |
+                        ID_AA64DFR0_EL1_TraceVer);
 
                /* Cap Debug to ARMv8.1 */
                val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, VHE);