#include "intel_hotplug.h"
 #include "intel_pch_display.h"
 #include "intel_pps.h"
-#include "vlv_sideband.h"
 
 static const struct dpll g4x_dpll[] = {
        { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
                                const struct intel_crtc_state *old_crtc_state,
                                const struct drm_connector_state *old_conn_state)
 {
-       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
        intel_dp_link_down(encoder, old_crtc_state);
 
-       vlv_dpio_get(dev_priv);
-
        /* Assert data lane reset */
        chv_data_lane_soft_reset(encoder, old_crtc_state, true);
-
-       vlv_dpio_put(dev_priv);
 }
 
 static void
 
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_sdvo.h"
-#include "vlv_sideband.h"
 
 static void intel_hdmi_prepare(struct intel_encoder *encoder,
                               const struct intel_crtc_state *crtc_state)
                                  const struct intel_crtc_state *old_crtc_state,
                                  const struct drm_connector_state *old_conn_state)
 {
-       struct intel_display *display = to_intel_display(encoder);
-       struct drm_i915_private *dev_priv = to_i915(display->drm);
-
-       vlv_dpio_get(dev_priv);
-
        /* Assert data lane reset */
        chv_data_lane_soft_reset(encoder, old_crtc_state, true);
-
-       vlv_dpio_put(dev_priv);
 }
 
 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 
        vlv_dpio_put(dev_priv);
 }
 
-void chv_data_lane_soft_reset(struct intel_encoder *encoder,
-                             const struct intel_crtc_state *crtc_state,
-                             bool reset)
+static void __chv_data_lane_soft_reset(struct intel_encoder *encoder,
+                                      const struct intel_crtc_state *crtc_state,
+                                      bool reset)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
        }
 }
 
+void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *crtc_state,
+                             bool reset)
+{
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+       vlv_dpio_get(i915);
+       __chv_data_lane_soft_reset(encoder, crtc_state, reset);
+       vlv_dpio_put(i915);
+}
+
 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
                            const struct intel_crtc_state *crtc_state)
 {
        vlv_dpio_get(dev_priv);
 
        /* Assert data lane reset */
-       chv_data_lane_soft_reset(encoder, crtc_state, true);
+       __chv_data_lane_soft_reset(encoder, crtc_state, true);
 
        /* program left/right clock distribution */
        if (pipe != PIPE_B) {
        }
 
        /* Deassert data lane reset */
-       chv_data_lane_soft_reset(encoder, crtc_state, false);
+       __chv_data_lane_soft_reset(encoder, crtc_state, false);
 
        vlv_dpio_put(dev_priv);
 }