Merge tag 'x86-urgent-2024-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 fixes from Ingo Molnar:
 "Fix TDX MMIO #VE fault handling, and add two new Intel model numbers
  for 'Pantherlake' and 'Diamond Rapids'"

* tag 'x86-urgent-2024-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Add two Intel CPU model numbers
  x86/tdx: Fix "in-kernel MMIO" check

diff --cc arch/x86/include/asm/intel-family.h
index 44949f972826ec8423cec67b9b5265fba2783921,17d899da465028da08c70d6e164780a93f6fdb8a..1a42f829667a37d65e96221c4a79e7d9f699e7a7
--- 1/arch/x86/include/asm/intel-family.h
--- 2/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@@ -117,42 -161,69 +117,44 @@@
  
  /* "Hybrid" Processors (P-Core/E-Core) */
  
 -#define INTEL_FAM6_LAKEFIELD          0x8A    /* Sunny Cove / Tremont */
  #define INTEL_LAKEFIELD                       IFM(6, 0x8A) /* Sunny Cove / Tremont */
  
 -#define INTEL_FAM6_ALDERLAKE          0x97    /* Golden Cove / Gracemont */
  #define INTEL_ALDERLAKE                       IFM(6, 0x97) /* Golden Cove / Gracemont */
 -#define INTEL_FAM6_ALDERLAKE_L                0x9A    /* Golden Cove / Gracemont */
  #define INTEL_ALDERLAKE_L             IFM(6, 0x9A) /* Golden Cove / Gracemont */
  
 -#define INTEL_FAM6_RAPTORLAKE         0xB7    /* Raptor Cove / Enhanced Gracemont */
  #define INTEL_RAPTORLAKE              IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
 -#define INTEL_FAM6_RAPTORLAKE_P               0xBA
  #define INTEL_RAPTORLAKE_P            IFM(6, 0xBA)
 -#define INTEL_FAM6_RAPTORLAKE_S               0xBF
  #define INTEL_RAPTORLAKE_S            IFM(6, 0xBF)
  
 -#define INTEL_FAM6_METEORLAKE         0xAC
  #define INTEL_METEORLAKE              IFM(6, 0xAC)
 -#define INTEL_FAM6_METEORLAKE_L               0xAA
  #define INTEL_METEORLAKE_L            IFM(6, 0xAA)
  
 -#define INTEL_FAM6_ARROWLAKE_H                0xC5
  #define INTEL_ARROWLAKE_H             IFM(6, 0xC5)
 -#define INTEL_FAM6_ARROWLAKE          0xC6
  #define INTEL_ARROWLAKE                       IFM(6, 0xC6)
 -#define INTEL_FAM6_ARROWLAKE_U                0xB5
  #define INTEL_ARROWLAKE_U             IFM(6, 0xB5)
  
 -#define INTEL_FAM6_LUNARLAKE_M                0xBD
  #define INTEL_LUNARLAKE_M             IFM(6, 0xBD)
  
+ #define INTEL_PANTHERLAKE_L           IFM(6, 0xCC)
+ 
  /* "Small Core" Processors (Atom/E-Core) */
  
 -#define INTEL_FAM6_ATOM_BONNELL               0x1C /* Diamondville, Pineview */
  #define INTEL_ATOM_BONNELL            IFM(6, 0x1C) /* Diamondville, Pineview */
 -#define INTEL_FAM6_ATOM_BONNELL_MID   0x26 /* Silverthorne, Lincroft */
  #define INTEL_ATOM_BONNELL_MID                IFM(6, 0x26) /* Silverthorne, Lincroft */
  
 -#define INTEL_FAM6_ATOM_SALTWELL      0x36 /* Cedarview */
  #define INTEL_ATOM_SALTWELL           IFM(6, 0x36) /* Cedarview */
 -#define INTEL_FAM6_ATOM_SALTWELL_MID  0x27 /* Penwell */
  #define INTEL_ATOM_SALTWELL_MID               IFM(6, 0x27) /* Penwell */
 -#define INTEL_FAM6_ATOM_SALTWELL_TABLET       0x35 /* Cloverview */
  #define INTEL_ATOM_SALTWELL_TABLET    IFM(6, 0x35) /* Cloverview */
  
 -#define INTEL_FAM6_ATOM_SILVERMONT    0x37 /* Bay Trail, Valleyview */
  #define INTEL_ATOM_SILVERMONT         IFM(6, 0x37) /* Bay Trail, Valleyview */
 -#define INTEL_FAM6_ATOM_SILVERMONT_D  0x4D /* Avaton, Rangely */
  #define INTEL_ATOM_SILVERMONT_D               IFM(6, 0x4D) /* Avaton, Rangely */
 -#define INTEL_FAM6_ATOM_SILVERMONT_MID        0x4A /* Merriefield */
  #define INTEL_ATOM_SILVERMONT_MID     IFM(6, 0x4A) /* Merriefield */
  
 -#define INTEL_FAM6_ATOM_AIRMONT               0x4C /* Cherry Trail, Braswell */
  #define INTEL_ATOM_AIRMONT            IFM(6, 0x4C) /* Cherry Trail, Braswell */
 -#define INTEL_FAM6_ATOM_AIRMONT_MID   0x5A /* Moorefield */
  #define INTEL_ATOM_AIRMONT_MID                IFM(6, 0x5A) /* Moorefield */
 -#define INTEL_FAM6_ATOM_AIRMONT_NP    0x75 /* Lightning Mountain */
  #define INTEL_ATOM_AIRMONT_NP         IFM(6, 0x75) /* Lightning Mountain */
  
 -#define INTEL_FAM6_ATOM_GOLDMONT      0x5C /* Apollo Lake */
  #define INTEL_ATOM_GOLDMONT           IFM(6, 0x5C) /* Apollo Lake */
 -#define INTEL_FAM6_ATOM_GOLDMONT_D    0x5F /* Denverton */
  #define INTEL_ATOM_GOLDMONT_D         IFM(6, 0x5F) /* Denverton */
  
  /* Note: the micro-architecture is "Goldmont Plus" */