#define I40E_MIN_VSI_ALLOC             83 /* LAN, ATR, FCOE, 64 VF */
 /* max 16 qps */
 #define i40e_default_queues_per_vmdq(pf) \
-               (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
+               (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
 #define I40E_DEFAULT_QUEUES_PER_VF     4
 #define I40E_DEFAULT_QUEUES_PER_TC     1 /* should be a power of 2 */
 #define i40e_pf_get_max_q_per_tc(pf) \
-               (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
+               (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
 #define I40E_FDIR_RING                 0
 #define I40E_FDIR_RING_COUNT           32
 #define I40E_MAX_AQ_BUF_SIZE           4096
        struct timer_list service_timer;
        struct work_struct service_task;
 
+       u64 hw_features;
+#define I40E_HW_RSS_AQ_CAPABLE                 BIT_ULL(0)
+#define I40E_HW_128_QP_RSS_CAPABLE             BIT_ULL(1)
+#define I40E_HW_ATR_EVICT_CAPABLE              BIT_ULL(2)
+#define I40E_HW_WB_ON_ITR_CAPABLE              BIT_ULL(3)
+#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE    BIT_ULL(4)
+#define I40E_HW_NO_PCI_LINK_CHECK              BIT_ULL(5)
+#define I40E_HW_100M_SGMII_CAPABLE             BIT_ULL(6)
+#define I40E_HW_NO_DCB_SUPPORT                 BIT_ULL(7)
+#define I40E_HW_USE_SET_LLDP_MIB               BIT_ULL(8)
+#define I40E_HW_GENEVE_OFFLOAD_CAPABLE         BIT_ULL(9)
+#define I40E_HW_PTP_L4_CAPABLE                 BIT_ULL(10)
+#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE          BIT_ULL(11)
+#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE       BIT_ULL(12)
+#define I40E_HW_HAVE_CRT_RETIMER               BIT_ULL(13)
+#define I40E_HW_OUTER_UDP_CSUM_CAPABLE         BIT_ULL(14)
+#define I40E_HW_PHY_CONTROLS_LEDS              BIT_ULL(15)
+#define I40E_HW_STOP_FW_LLDP                   BIT_ULL(16)
+#define I40E_HW_PORT_ID_VALID                  BIT_ULL(17)
+#define I40E_HW_RESTART_AUTONEG                        BIT_ULL(18)
+
        u64 flags;
 #define I40E_FLAG_RX_CSUM_ENABLED              BIT_ULL(1)
 #define I40E_FLAG_MSI_ENABLED                  BIT_ULL(2)
 #define I40E_FLAG_PTP                          BIT_ULL(25)
 #define I40E_FLAG_MFP_ENABLED                  BIT_ULL(26)
 #define I40E_FLAG_UDP_FILTER_SYNC              BIT_ULL(27)
-#define I40E_FLAG_PORT_ID_VALID                        BIT_ULL(28)
 #define I40E_FLAG_DCB_CAPABLE                  BIT_ULL(29)
-#define I40E_FLAG_RSS_AQ_CAPABLE               BIT_ULL(31)
-#define I40E_FLAG_HW_ATR_EVICT_CAPABLE         BIT_ULL(32)
-#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE       BIT_ULL(33)
-#define I40E_FLAG_128_QP_RSS_CAPABLE           BIT_ULL(34)
-#define I40E_FLAG_WB_ON_ITR_CAPABLE            BIT_ULL(35)
 #define I40E_FLAG_VEB_STATS_ENABLED            BIT_ULL(37)
-#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE  BIT_ULL(38)
 #define I40E_FLAG_LINK_POLLING_ENABLED         BIT_ULL(39)
 #define I40E_FLAG_VEB_MODE_ENABLED             BIT_ULL(40)
-#define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE       BIT_ULL(41)
-#define I40E_FLAG_NO_PCI_LINK_CHECK            BIT_ULL(42)
-#define I40E_FLAG_100M_SGMII_CAPABLE           BIT_ULL(43)
-#define I40E_FLAG_RESTART_AUTONEG              BIT_ULL(44)
-#define I40E_FLAG_NO_DCB_SUPPORT               BIT_ULL(45)
-#define I40E_FLAG_USE_SET_LLDP_MIB             BIT_ULL(46)
-#define I40E_FLAG_STOP_FW_LLDP                 BIT_ULL(47)
-#define I40E_FLAG_PHY_CONTROLS_LEDS            BIT_ULL(48)
 #define I40E_FLAG_PF_MAC                       BIT_ULL(50)
 #define I40E_FLAG_TRUE_PROMISC_SUPPORT         BIT_ULL(51)
-#define I40E_FLAG_HAVE_CRT_RETIMER             BIT_ULL(52)
-#define I40E_FLAG_PTP_L4_CAPABLE               BIT_ULL(53)
 #define I40E_FLAG_CLIENT_RESET                 BIT_ULL(54)
 #define I40E_FLAG_TEMP_LINK_POLLING            BIT_ULL(55)
 #define I40E_FLAG_CLIENT_L2_CHANGE             BIT_ULL(56)
-#define I40E_FLAG_WOL_MC_MAGIC_PKT_WAKE                BIT_ULL(57)
 #define I40E_FLAG_LEGACY_RX                    BIT_ULL(58)
 
        struct i40e_client_instance *cinst;
 
                *advertising |= ADVERTISED_Autoneg;
                if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
                        *advertising |= ADVERTISED_1000baseT_Full;
-               if (pf->flags & I40E_FLAG_100M_SGMII_CAPABLE) {
+               if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
                        *supported |= SUPPORTED_100baseT_Full;
                        *advertising |= ADVERTISED_100baseT_Full;
                }
                        *advertising |= ADVERTISED_20000baseKR2_Full;
        }
        if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR) {
-               if (!(pf->flags & I40E_FLAG_HAVE_CRT_RETIMER))
+               if (!(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER))
                        *supported |= SUPPORTED_10000baseKR_Full |
                                      SUPPORTED_Autoneg;
                *advertising |= ADVERTISED_Autoneg;
                if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
-                       if (!(pf->flags & I40E_FLAG_HAVE_CRT_RETIMER))
+                       if (!(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER))
                                *advertising |= ADVERTISED_10000baseKR_Full;
        }
        if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4) {
                        *advertising |= ADVERTISED_10000baseKX4_Full;
        }
        if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX) {
-               if (!(pf->flags & I40E_FLAG_HAVE_CRT_RETIMER))
+               if (!(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER))
                        *supported |= SUPPORTED_1000baseKX_Full |
                                      SUPPORTED_Autoneg;
                *advertising |= ADVERTISED_Autoneg;
                if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
-                       if (!(pf->flags & I40E_FLAG_HAVE_CRT_RETIMER))
+                       if (!(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER))
                                *advertising |= ADVERTISED_1000baseKX_Full;
        }
        if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
                            SUPPORTED_1000baseT_Full;
                if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
                        advertising |= ADVERTISED_1000baseT_Full;
-               if (pf->flags & I40E_FLAG_100M_SGMII_CAPABLE) {
+               if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
                        supported |= SUPPORTED_100baseT_Full;
                        if (hw_link_info->requested_speeds &
                            I40E_LINK_SPEED_100MB)
                           BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
                           BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
 
-       if (pf->flags & I40E_FLAG_PTP_L4_CAPABLE)
+       if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE)
                info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
                                    BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
                                    BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
 
        switch (state) {
        case ETHTOOL_ID_ACTIVE:
-               if (!(pf->flags & I40E_FLAG_PHY_CONTROLS_LEDS)) {
+               if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
                        pf->led_status = i40e_led_get(hw);
                } else {
                        i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL, NULL);
                }
                return blink_freq;
        case ETHTOOL_ID_ON:
-               if (!(pf->flags & I40E_FLAG_PHY_CONTROLS_LEDS))
+               if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
                        i40e_led_set(hw, 0xf, false);
                else
                        ret = i40e_led_set_phy(hw, true, pf->led_status, 0);
                break;
        case ETHTOOL_ID_OFF:
-               if (!(pf->flags & I40E_FLAG_PHY_CONTROLS_LEDS))
+               if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
                        i40e_led_set(hw, 0x0, false);
                else
                        ret = i40e_led_set_phy(hw, false, pf->led_status, 0);
                break;
        case ETHTOOL_ID_INACTIVE:
-               if (!(pf->flags & I40E_FLAG_PHY_CONTROLS_LEDS)) {
+               if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
                        i40e_led_set(hw, pf->led_status, false);
                } else {
                        ret = i40e_led_set_phy(hw, false, pf->led_status,
        switch (nfc->flow_type) {
        case TCP_V4_FLOW:
                flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
-               if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
+               if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
                        hena |=
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
                break;
        case TCP_V6_FLOW:
                flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
-               if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
+               if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
                        hena |=
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
-               if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
+               if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
                        hena |=
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
                break;
        case UDP_V4_FLOW:
                flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
-               if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
+               if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
                        hena |=
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
                break;
        case UDP_V6_FLOW:
                flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
-               if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE)
+               if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
                        hena |=
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
                          BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
        }
 
        /* Only allow ATR evict on hardware that is capable of handling it */
-       if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
+       if (!(pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE))
                pf->flags &= ~I40E_FLAG_HW_ATR_EVICT_ENABLED;
 
        if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {
 
        int err = 0;
 
        /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
-       if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
+       if (pf->hw_features & I40E_HW_NO_DCB_SUPPORT)
                goto out;
 
        /* Get the initial DCB configuration */
                wr32(hw, I40E_REG_MSS, val);
        }
 
-       if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
+       if (pf->hw_features & I40E_HW_RESTART_AUTONEG) {
                msleep(75);
                ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
                if (ret)
                ring->count = vsi->num_desc;
                ring->size = 0;
                ring->dcb_tc = 0;
-               if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
+               if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
                        ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
                ring->tx_itr_setting = pf->tx_itr_default;
                vsi->tx_rings[i] = ring++;
                ring->count = vsi->num_desc;
                ring->size = 0;
                ring->dcb_tc = 0;
-               if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
+               if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
                        ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
                set_ring_xdp(ring);
                ring->tx_itr_setting = pf->tx_itr_default;
        u8 *lut;
        int ret;
 
-       if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
+       if (!(pf->hw_features & I40E_HW_RSS_AQ_CAPABLE))
                return 0;
 
        if (!vsi->rss_size)
 {
        struct i40e_pf *pf = vsi->back;
 
-       if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
+       if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)
                return i40e_config_rss_aq(vsi, seed, lut, lut_size);
        else
                return i40e_config_rss_reg(vsi, seed, lut, lut_size);
 {
        struct i40e_pf *pf = vsi->back;
 
-       if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
+       if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)
                return i40e_get_rss_aq(vsi, seed, lut, lut_size);
        else
                return i40e_get_rss_reg(vsi, seed, lut, lut_size);
        }
 
        if (pf->hw.mac.type == I40E_MAC_X722) {
-               pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE
-                            | I40E_FLAG_128_QP_RSS_CAPABLE
-                            | I40E_FLAG_HW_ATR_EVICT_CAPABLE
-                            | I40E_FLAG_OUTER_UDP_CSUM_CAPABLE
-                            | I40E_FLAG_WB_ON_ITR_CAPABLE
-                            | I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE
-                            | I40E_FLAG_NO_PCI_LINK_CHECK
-                            | I40E_FLAG_USE_SET_LLDP_MIB
-                            | I40E_FLAG_GENEVE_OFFLOAD_CAPABLE
-                            | I40E_FLAG_PTP_L4_CAPABLE
-                            | I40E_FLAG_WOL_MC_MAGIC_PKT_WAKE;
+               pf->hw_features |= (I40E_HW_RSS_AQ_CAPABLE |
+                                   I40E_HW_128_QP_RSS_CAPABLE |
+                                   I40E_HW_ATR_EVICT_CAPABLE |
+                                   I40E_HW_WB_ON_ITR_CAPABLE |
+                                   I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE |
+                                   I40E_HW_NO_PCI_LINK_CHECK |
+                                   I40E_HW_USE_SET_LLDP_MIB |
+                                   I40E_HW_GENEVE_OFFLOAD_CAPABLE |
+                                   I40E_HW_PTP_L4_CAPABLE |
+                                   I40E_HW_WOL_MC_MAGIC_PKT_WAKE |
+                                   I40E_HW_OUTER_UDP_CSUM_CAPABLE);
        } else if ((pf->hw.aq.api_maj_ver > 1) ||
                   ((pf->hw.aq.api_maj_ver == 1) &&
                    (pf->hw.aq.api_min_ver > 4))) {
                /* Supported in FW API version higher than 1.4 */
-               pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
+               pf->hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE;
        }
 
        /* Enable HW ATR eviction if possible */
-       if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
+       if (pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE)
                pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED;
 
        if ((pf->hw.mac.type == I40E_MAC_XL710) &&
            (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
            (pf->hw.aq.fw_maj_ver < 4))) {
-               pf->flags |= I40E_FLAG_RESTART_AUTONEG;
+               pf->hw_features |= I40E_HW_RESTART_AUTONEG;
                /* No DCB support  for FW < v4.33 */
-               pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
+               pf->hw_features |= I40E_HW_NO_DCB_SUPPORT;
        }
 
        /* Disable FW LLDP if FW < v4.3 */
        if ((pf->hw.mac.type == I40E_MAC_XL710) &&
            (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
            (pf->hw.aq.fw_maj_ver < 4)))
-               pf->flags |= I40E_FLAG_STOP_FW_LLDP;
+               pf->hw_features |= I40E_HW_STOP_FW_LLDP;
 
        /* Use the FW Set LLDP MIB API if FW > v4.40 */
        if ((pf->hw.mac.type == I40E_MAC_XL710) &&
            (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
            (pf->hw.aq.fw_maj_ver >= 5)))
-               pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
+               pf->hw_features |= I40E_HW_USE_SET_LLDP_MIB;
 
        if (pf->hw.func_caps.vmdq) {
                pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
                pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
                break;
        case UDP_TUNNEL_TYPE_GENEVE:
-               if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
+               if (!(pf->hw_features & I40E_HW_GENEVE_OFFLOAD_CAPABLE))
                        return;
                pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
                break;
        struct i40e_pf *pf = np->vsi->back;
        struct i40e_hw *hw = &pf->hw;
 
-       if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
+       if (!(pf->hw_features & I40E_HW_PORT_ID_VALID))
                return -EOPNOTSUPP;
 
        ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
                          NETIF_F_RXCSUM                |
                          0;
 
-       if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE))
+       if (!(pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE))
                netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
 
        netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
                break;
        }
 
-       if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
+       if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) &&
            (vsi->type == I40E_VSI_VMDQ2)) {
                ret = i40e_vsi_config_rss(vsi);
        }
         * Ignore error return codes because if it was already disabled via
         * hardware settings this will fail
         */
-       if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
+       if (pf->hw_features & I40E_HW_STOP_FW_LLDP) {
                dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
                i40e_aq_stop_lldp(hw, true, NULL);
        }
        ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
        i40e_get_port_mac_addr(hw, hw->mac.port_addr);
        if (is_valid_ether_addr(hw->mac.port_addr))
-               pf->flags |= I40E_FLAG_PORT_ID_VALID;
+               pf->hw_features |= I40E_HW_PORT_ID_VALID;
 
        pci_set_drvdata(pdev, pf);
        pci_save_state(pdev);
                wr32(hw, I40E_REG_MSS, val);
        }
 
-       if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
+       if (pf->hw_features & I40E_HW_RESTART_AUTONEG) {
                msleep(75);
                err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
                if (err)
         * and will report PCI Gen 1 x 1 by default so don't bother
         * checking them.
         */
-       if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
+       if (!(pf->hw_features & I40E_HW_NO_PCI_LINK_CHECK)) {
                char speed[PCI_SPEED_SIZE] = "Unknown";
                char width[PCI_WIDTH_SIZE] = "Unknown";
 
 
        if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
                (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
-               pf->flags |= I40E_FLAG_PHY_CONTROLS_LEDS;
+               pf->hw_features |= I40E_HW_PHY_CONTROLS_LEDS;
        if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722)
-               pf->flags |= I40E_FLAG_HAVE_CRT_RETIMER;
+               pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;
        /* print a string summarizing features */
        i40e_print_features(pf);
 
         */
        i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
 
-       if (pf->wol_en && (pf->flags & I40E_FLAG_WOL_MC_MAGIC_PKT_WAKE))
+       if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE))
                i40e_enable_mc_magic_wake(pf);
 
        i40e_prep_for_reset(pf, false);
        set_bit(__I40E_SUSPENDED, pf->state);
        set_bit(__I40E_DOWN, pf->state);
 
-       if (pf->wol_en && (pf->flags & I40E_FLAG_WOL_MC_MAGIC_PKT_WAKE))
+       if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE))
                i40e_enable_mc_magic_wake(pf);
 
        i40e_prep_for_reset(pf, false);
 
        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
        case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
-               if (!(pf->flags & I40E_FLAG_PTP_L4_CAPABLE))
+               if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
                        return -ERANGE;
                pf->ptp_rx = true;
                tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
        case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
        case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
        case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
-               if (!(pf->flags & I40E_FLAG_PTP_L4_CAPABLE))
+               if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
                        return -ERANGE;
                /* fall through */
        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
                pf->ptp_rx = true;
                tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
                           I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
-               if (pf->flags & I40E_FLAG_PTP_L4_CAPABLE) {
+               if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
                        tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
                        config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
                } else {
 
        BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
 
 #define i40e_pf_get_default_rss_hena(pf) \
-       (((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
+       (((pf)->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
          I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)
 
 /* Supported Rx Buffer Sizes (a multiple of 128) */
 
        if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
                vfres->vf_offload_flags |= VIRTCHNL_VF_OFFLOAD_RSS_PF;
        } else {
-               if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
+               if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) &&
                    (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_AQ))
                        vfres->vf_offload_flags |= VIRTCHNL_VF_OFFLOAD_RSS_AQ;
                else
                        vfres->vf_offload_flags |= VIRTCHNL_VF_OFFLOAD_RSS_REG;
        }
 
-       if (pf->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) {
+       if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) {
                if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2)
                        vfres->vf_offload_flags |=
                                VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2;
        if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ENCAP)
                vfres->vf_offload_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP;
 
-       if ((pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
+       if ((pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE) &&
            (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM))
                vfres->vf_offload_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM;
 
                vfres->vf_offload_flags |= VIRTCHNL_VF_OFFLOAD_RX_POLLING;
        }
 
-       if (pf->flags & I40E_FLAG_WB_ON_ITR_CAPABLE) {
+       if (pf->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) {
                if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_WB_ON_ITR)
                        vfres->vf_offload_flags |=
                                        VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;
 
        BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
        BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
 
-#define i40e_pf_get_default_rss_hena(pf) \
-       (((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
-         I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)
-
 /* Supported Rx Buffer Sizes (a multiple of 128) */
 #define I40E_RXBUFFER_256   256
 #define I40E_RXBUFFER_1536  1536  /* 128B aligned standard Ethernet frame */
 
 /* duplicates for common code */
 #define I40E_FLAG_DCB_ENABLED                  0
 #define I40E_FLAG_RX_CSUM_ENABLED              I40EVF_FLAG_RX_CSUM_ENABLED
-#define I40E_FLAG_WB_ON_ITR_CAPABLE            I40EVF_FLAG_WB_ON_ITR_CAPABLE
-#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE       I40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE
 #define I40E_FLAG_LEGACY_RX                    I40EVF_FLAG_LEGACY_RX
        /* flags for admin queue service task */
        u32 aq_required;
 
                tx_ring->dev = &adapter->pdev->dev;
                tx_ring->count = adapter->tx_desc_count;
                tx_ring->tx_itr_setting = (I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF);
-               if (adapter->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
+               if (adapter->flags & I40EVF_FLAG_WB_ON_ITR_CAPABLE)
                        tx_ring->flags |= I40E_TXR_FLAGS_WB_ON_ITR;
 
                rx_ring = &adapter->rx_rings[i];