Merge tag 'iommu-updates-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...

Pull iommu updates from Joerg Roedel:
 "Core changes:
   - iova_magazine_alloc() optimization
   - Make flush-queue an IOMMU driver capability
   - Consolidate the error handling around device attachment

  AMD IOMMU changes:
   - AVIC Interrupt Remapping Improvements
   - Some minor fixes and cleanups

  Intel VT-d changes from Lu Baolu:
   - Small and misc cleanups

  ARM-SMMU changes from Will Deacon:
   - Device-tree binding updates:
      - Add missing clocks for SC8280XP and SA8775 Adreno SMMUs
      - Add two new Qualcomm SMMUs in SDX75 and SM6375
   - Workarounds for Arm MMU-700 errata:
      - 1076982: Avoid use of SEV-based cmdq wakeup
      - 2812531: Terminate command batches with a CMD_SYNC
      - Enforce single-stage translation to avoid nesting-related errata
   - Set the correct level hint for range TLB invalidation on teardown

  .. and some other minor fixes and cleanups (including Freescale PAMU
  and virtio-iommu changes)"

* tag 'iommu-updates-v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (50 commits)
  iommu/vt-d: Remove commented-out code
  iommu/vt-d: Remove two WARN_ON in domain_context_mapping_one()
  iommu/vt-d: Handle the failure case of dmar_reenable_qi()
  iommu/vt-d: Remove unnecessary (void*) conversions
  iommu/amd: Remove extern from function prototypes
  iommu/amd: Use BIT/BIT_ULL macro to define bit fields
  iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro
  iommu/amd: Fix compile error for unused function
  iommu/amd: Improving Interrupt Remapping Table Invalidation
  iommu/amd: Do not Invalidate IRT when IRTE caching is disabled
  iommu/amd: Introduce Disable IRTE Caching Support
  iommu/amd: Remove the unused struct amd_ir_data.ref
  iommu/amd: Switch amd_iommu_update_ga() to use modify_irte_ga()
  iommu/arm-smmu-v3: Set TTL invalidation hint better
  iommu/arm-smmu-v3: Document nesting-related errata
  iommu/arm-smmu-v3: Add explicit feature for nesting
  iommu/arm-smmu-v3: Document MMU-700 erratum 2812531
  iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982
  dt-bindings: arm-smmu: Add SDX75 SMMU compatible
  dt-bindings: arm-smmu: Add SM6375 GPU SMMU
  ...

diff --cc Documentation/admin-guide/kernel-parameters.txt
Simple merge

diff --cc Documentation/arch/arm64/silicon-errata.rst
Simple merge

diff --cc drivers/iommu/amd/amd_iommu_types.h
Simple merge

diff --cc drivers/iommu/amd/iommu.c
index 9ea40960978be36445f1a204ec622ea080ab2ede,dc481080f7222964f0fe325da9f5b8f915a11b9e..c3b58a8389b9bff28db96b42289ff1af7db64dc6
--- 1/drivers/iommu/amd/iommu.c
--- 2/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@@ -3021,12 -3052,12 +3052,12 @@@ out
  }
  
  static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
-                         struct irte_ga *irte, struct amd_ir_data *data)
+                         struct irte_ga *irte)
  {
 -      bool ret;
        struct irq_remap_table *table;
 -      unsigned long flags;
        struct irte_ga *entry;
 +      unsigned long flags;
 +      u128 old;
  
        table = get_irq_table(iommu, devid);
        if (!table)
@@@ -3043,16 -3077,11 +3074,12 @@@
         * behind us, so the return value of cmpxchg16 should be the
         * same as the old value.
         */
 -      WARN_ON(!ret);
 +      old = entry->irte;
 +      WARN_ON(!try_cmpxchg128(&entry->irte, &old, irte->irte));
  
-       if (data)
-               data->ref = entry;
- 
        raw_spin_unlock_irqrestore(&table->lock, flags);
  
-       iommu_flush_irt(iommu, devid);
-       iommu_completion_wait(iommu);
+       iommu_flush_irt_and_complete(iommu, devid);
  
        return 0;
  }

diff --cc drivers/iommu/dma-iommu.c
Simple merge

diff --cc drivers/iommu/iommu.c
Simple merge