ARM: dts: microchip: sam9x60: Fix rtc/rtt clocks

The RTC and RTT peripherals use the timing domain slow clock (TD_SLCK),
sourced from the 32.768 kHz crystal oscillator or slow rc oscillator.

The previously used Monitoring domain slow clock (MD_SLCK) is sourced
from an internal RC oscillator which is most probably not precise enough
for real time clock purposes.

Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Fixes: 5f6b33f46346 ("ARM: dts: sam9x60: add rtt")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20240821055136.6858-1-ada@thorsis.com
[claudiu.beznea: removed () around the last commit description paragraph,
 removed " in front of "timing domain slow clock", described that
 TD_SLCK can also be sourced from slow rc oscillator]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index 76d467cc2892ce15720cd6200fdf3bf6b184c89e..04a6d716ecaf8a07253190bb278a608135f9cac9 100644 (file)
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -1338,7 +1338,7 @@
                                compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
                                reg = <0xfffffe20 0x20>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-                               clocks = <&clk32k 0>;
+                               clocks = <&clk32k 1>;
                        };
 
                        pit: timer@fffffe40 {
@@ -1364,7 +1364,7 @@
                                compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
                                reg = <0xfffffea8 0x100>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-                               clocks = <&clk32k 0>;
+                               clocks = <&clk32k 1>;
                        };
 
                        watchdog: watchdog@ffffff80 {