}
 }
 
+static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
+{
+       u32                     reg;
+       struct device_node      *node = omap->dev->of_node;
+       int                     utmi_mode = 0;
+
+       reg = dwc3_omap_read_utmi_status(omap);
+
+       of_property_read_u32(node, "utmi-mode", &utmi_mode);
+
+       switch (utmi_mode) {
+       case DWC3_OMAP_UTMI_MODE_SW:
+               reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
+               break;
+       case DWC3_OMAP_UTMI_MODE_HW:
+               reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
+               break;
+       default:
+               dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
+       }
+
+       dwc3_omap_write_utmi_status(omap, reg);
+}
+
 static int dwc3_omap_probe(struct platform_device *pdev)
 {
        struct device_node      *node = pdev->dev.of_node;
        int                     ret;
        int                     irq;
 
-       int                     utmi_mode = 0;
-
        u32                     reg;
 
        void __iomem            *base;
        }
 
        dwc3_omap_map_offset(omap);
-
-       reg = dwc3_omap_read_utmi_status(omap);
-
-       of_property_read_u32(node, "utmi-mode", &utmi_mode);
-
-       switch (utmi_mode) {
-       case DWC3_OMAP_UTMI_MODE_SW:
-               reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
-               break;
-       case DWC3_OMAP_UTMI_MODE_HW:
-               reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
-               break;
-       default:
-               dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
-       }
-
-       dwc3_omap_write_utmi_status(omap, reg);
+       dwc3_omap_set_utmi_mode(omap);
 
        /* check the DMA Status */
        reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);