}
 
                if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
-                       err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
+                       err = mv88e6xxx_g1_vtu_sid_read(chip, &next);
                        if (err)
                                return err;
-
-                       next.sid = val & GLOBAL_VTU_SID_MASK;
                }
        }
 
                return err;
 
        if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
-               reg = entry->sid & GLOBAL_VTU_SID_MASK;
-               err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
+               err = mv88e6xxx_g1_vtu_sid_write(chip, entry);
                if (err)
                        return err;
        }
 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
                                  struct mv88e6xxx_vtu_entry *entry)
 {
-       struct mv88e6xxx_vtu_entry next = { 0 };
+       struct mv88e6xxx_vtu_entry next = {
+               .sid = sid,
+       };
        u16 val;
        int err;
 
        if (err)
                return err;
 
-       err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
-                                sid & GLOBAL_VTU_SID_MASK);
+       err = mv88e6xxx_g1_vtu_sid_write(chip, &next);
        if (err)
                return err;
 
        if (err)
                return err;
 
-       err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
+       err = mv88e6xxx_g1_vtu_sid_read(chip, &next);
        if (err)
                return err;
 
-       next.sid = val & GLOBAL_VTU_SID_MASK;
-
        err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
        if (err)
                return err;
        if (err)
                return err;
 
-       reg = entry->sid & GLOBAL_VTU_SID_MASK;
-       err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
+       err = mv88e6xxx_g1_vtu_sid_write(chip, entry);
        if (err)
                return err;
 
 
                              struct mv88e6xxx_vtu_entry *entry);
 int mv88e6xxx_g1_vtu_fid_write(struct mv88e6xxx_chip *chip,
                               struct mv88e6xxx_vtu_entry *entry);
+int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip,
+                             struct mv88e6xxx_vtu_entry *entry);
+int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip,
+                              struct mv88e6xxx_vtu_entry *entry);
 int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip);
 int mv88e6xxx_g1_vtu_op(struct mv88e6xxx_chip *chip, u16 op);
 int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
 
        return mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, val);
 }
 
+/* Offset 0x03: VTU SID Register */
+
+int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip,
+                             struct mv88e6xxx_vtu_entry *entry)
+{
+       u16 val;
+       int err;
+
+       err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
+       if (err)
+               return err;
+
+       entry->sid = val & GLOBAL_VTU_SID_MASK;
+
+       return 0;
+}
+
+int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip,
+                              struct mv88e6xxx_vtu_entry *entry)
+{
+       u16 val = entry->sid & GLOBAL_VTU_SID_MASK;
+
+       return mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, val);
+}
+
 /* Offset 0x05: VTU Operation Register */
 
 int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip)