drm/amd/display: Enabled pipe harvesting in dcn30

[Why & How]
Ported logic from dcn21 for reading in pipe fusing to dcn30.
Supported configurations are 1 and 6 pipes. Invalid fusing
will revert to 1 pipe being enabled.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 8d0f663489ac5a915330f7f1d689d299daed647f..fb7f1dea3c467e4f33aaf1228a9d62f7e3da2fd3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2508,6 +2508,19 @@ static const struct resource_funcs dcn30_res_pool_funcs = {
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
 };
 
+#define CTX ctx
+
+#define REG(reg_name) \
+       (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+       uint32_t value = REG_READ(CC_DC_PIPE_DIS);
+       /* Support for max 6 pipes */
+       value = value & 0x3f;
+       return value;
+}
+
 static bool dcn30_resource_construct(
        uint8_t num_virtual_links,
        struct dc *dc,
@@ -2517,6 +2530,15 @@ static bool dcn30_resource_construct(
        struct dc_context *ctx = dc->ctx;
        struct irq_service_init_data init_data;
        struct ddc_service_init_data ddc_init_data;
+       uint32_t pipe_fuses = read_pipe_fuses(ctx);
+       uint32_t num_pipes = 0;
+
+       if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
+               BREAK_TO_DEBUGGER();
+               dm_error("DC: Unexpected fuse recipe for navi2x !\n");
+               /* fault to single pipe */
+               pipe_fuses = 0x3e;
+       }
 
        DC_FP_START();
 
@@ -2650,6 +2672,15 @@ static bool dcn30_resource_construct(
        /* PP Lib and SMU interfaces */
        init_soc_bounding_box(dc, pool);
 
+       num_pipes = dcn3_0_ip.max_num_dpp;
+
+       for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
+               if (pipe_fuses & 1 << i)
+                       num_pipes--;
+
+       dcn3_0_ip.max_num_dpp = num_pipes;
+       dcn3_0_ip.max_num_otg = num_pipes;
+
        dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
 
        /* IRQ */