INTEL_ADLP_IDS(&gen11_early_ops),
INTEL_ADLN_IDS(&gen11_early_ops),
INTEL_RPLS_IDS(&gen11_early_ops),
+ INTEL_RPLU_IDS(&gen11_early_ops),
INTEL_RPLP_IDS(&gen11_early_ops),
};
INTEL_RPLS_IDS(&adl_s_display),
INTEL_ADLP_IDS(&xe_lpd_display),
INTEL_ADLN_IDS(&xe_lpd_display),
+ INTEL_RPLU_IDS(&xe_lpd_display),
INTEL_RPLP_IDS(&xe_lpd_display),
INTEL_DG2_IDS(&xe_hpd_display),
INTEL_ADLN_IDS(&adl_p_info),
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
+ INTEL_RPLU_IDS(&adl_p_info),
INTEL_RPLP_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
INTEL_ATS_M_IDS(&ats_m_info),
static const u16 subplatform_rpl_ids[] = {
INTEL_RPLS_IDS(0),
+ INTEL_RPLU_IDS(0),
INTEL_RPLP_IDS(0),
};
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
- INTEL_RPLU_IDS(info), \
INTEL_VGA_DEVICE(0xA720, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
INTEL_VGA_DEVICE(0xA7A8, info), \