*/
 static const struct drm_bridge_timings default_dac_timings = {
        /* Timing specifications, datasheet page 7 */
-       .sampling_edge = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
+       .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
        .setup_time_ps = 500,
        .hold_time_ps = 1500,
 };
  */
 static const struct drm_bridge_timings ti_ths8134_dac_timings = {
        /* From timing diagram, datasheet page 9 */
-       .sampling_edge = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
+       .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
        /* From datasheet, page 12 */
        .setup_time_ps = 3000,
        /* I guess this means latched input */
  */
 static const struct drm_bridge_timings ti_ths8135_dac_timings = {
        /* From timing diagram, datasheet page 14 */
-       .sampling_edge = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
+       .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
        /* From datasheet, page 16 */
        .setup_time_ps = 2000,
        .hold_time_ps = 500,
 
  */
 struct drm_bridge_timings {
        /**
-        * @sampling_edge:
+        * @input_bus_flags:
         *
-        * Tells whether the bridge samples the digital input signals from the
-        * display engine on the positive or negative edge of the clock. This
-        * should use the DRM_BUS_FLAG_PIXDATA_SAMPLE_[POS|NEG]EDGE and
-        * DRM_BUS_FLAG_SYNC_SAMPLE_[POS|NEG]EDGE bitwise flags from the DRM
-        * connector (bit 2, 3, 6 and 7 valid).
+        * Tells what additional settings for the pixel data on the bus
+        * this bridge requires (like pixel signal polarity). See also
+        * &drm_display_info->bus_flags.
         */
-       u32 sampling_edge;
+       u32 input_bus_flags;
        /**
         * @setup_time_ps:
         *