#define SDHCI_CLK_DELAY_SETTING 0x4C
 #define SDHCI_SIRF_8BITBUS BIT(3)
-#define SIRF_TUNING_COUNT 128
+#define SIRF_TUNING_COUNT 16384
 
 struct sdhci_sirf_priv {
        int gpio_cd;
 static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
 {
        int tuning_seq_cnt = 3;
-       u8 phase, tuned_phases[SIRF_TUNING_COUNT];
+       int phase;
        u8 tuned_phase_cnt = 0;
        int rc = 0, longest_range = 0;
        int start = -1, end = 0, tuning_value = -1, range = 0;
 
 retry:
        phase = 0;
+       tuned_phase_cnt = 0;
        do {
                sdhci_writel(host,
                        clock_setting | phase,
 
                if (!mmc_send_tuning(mmc)) {
                        /* Tuning is successful at this tuning point */
-                       tuned_phases[tuned_phase_cnt++] = phase;
+                       tuned_phase_cnt++;
                        dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
                                 mmc_hostname(mmc), phase);
                        if (start == -1)
                        start = -1;
                        end = range = 0;
                }
-       } while (++phase < ARRAY_SIZE(tuned_phases));
+       } while (++phase < SIRF_TUNING_COUNT);
 
        if (tuned_phase_cnt && tuning_value > 0) {
                /*