drm/i915/display: Implement wa_16011342517

While doing voltage swing for type-c phy
for DP 1.62 and HDMI write the
LOADGEN_SHARING_PMD_DISABLE bit to 1.

-v2: Update commit.
     Add bspec[Suraj]
-v3: Move w/a before DKL_TX_PMD_LANE_SUS.
     Use DKL_TX_DPCNTL2[Ville]
-v4: Use intel_encoder_is_dp and
     intel_encoder_is_hdmi. [Suraj]

Bspec: 55359
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250625074911.194085-1-nemesa.garg@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 36aa6d14589d37614fe13ba15baf4c7e60014e2c..0405396c7750eaf40dd35e25327b2d282c208c28 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -79,6 +79,7 @@
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
+#include "intel_step.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
@@ -1395,6 +1396,21 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
        for (ln = 0; ln < 2; ln++) {
                int level;
 
+               /* Wa_16011342517:adl-p */
+               if (display->platform.alderlake_p &&
+                   IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
+                       if ((intel_encoder_is_hdmi(encoder) &&
+                            crtc_state->port_clock == 594000) ||
+                            (intel_encoder_is_dp(encoder) &&
+                             crtc_state->port_clock == 162000)) {
+                               intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
+                                                 LOADGEN_SHARING_PMD_DISABLE, 1);
+                       } else {
+                               intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
+                                                 LOADGEN_SHARING_PMD_DISABLE, 0);
+                       }
+               }
+
                intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
 
                level = intel_ddi_level(encoder, crtc_state, 2*ln+0);

diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
index 3d8fa667cc7362383bac2f326204bca257aace94..f8ffeec29e933eb9a205ed0466f1ddf0abb191e4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
@@ -153,6 +153,7 @@ struct intel_dkl_phy_reg {
 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)     REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK     REG_GENMASK(6, 5)
 #define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)     REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
+#define  LOADGEN_SHARING_PMD_DISABLE                   REG_BIT(12)
 
 #define _DKL_TX_FW_CALIB_LN0                           0x02F8
 #define _DKL_TX_FW_CALIB_LN1                           0x12F8