phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()

While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk
support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set
on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
the frequency of the reference clock for the USB2.0 phy instead.

I stumbled across this while adding support for the Google Tensor
gs101, but this should apply to E850 just the same.

Do so.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 1da7a4881f7264f204a8ae9b96933b0a6f14cc12..15be966b50aeb8f5164db666cbbd0026ad5b9ec6 100644 (file)
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -8,6 +8,7 @@
  * Author: Vivek Gautam <gautam.vivek@samsung.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -141,6 +142,9 @@
 #define CLKRST_PORT_RST                                BIT(1)
 #define CLKRST_LINK_SW_RST                     BIT(0)
 
+#define EXYNOS850_DRD_SSPPLLCTL                        0x30
+#define SSPPLLCTL_FSEL                         GENMASK(2, 0)
+
 #define EXYNOS850_DRD_UTMI                     0x50
 #define UTMI_FORCE_VBUSVALID                   BIT(5)
 #define UTMI_FORCE_BVALID                      BIT(4)
@@ -773,6 +777,31 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
        reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL;
        writel(reg, regs_base + EXYNOS850_DRD_HSP);
 
+       reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL);
+       reg &= ~SSPPLLCTL_FSEL;
+       switch (phy_drd->extrefclk) {
+       case EXYNOS5_FSEL_50MHZ:
+               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
+               break;
+       case EXYNOS5_FSEL_26MHZ:
+               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6);
+               break;
+       case EXYNOS5_FSEL_24MHZ:
+               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2);
+               break;
+       case EXYNOS5_FSEL_20MHZ:
+               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1);
+               break;
+       case EXYNOS5_FSEL_19MHZ2:
+               reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0);
+               break;
+       default:
+               dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
+                        phy_drd->extrefclk);
+               break;
+       }
+       writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
+
        /* Power up PHY analog blocks */
        reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
        reg &= ~HSP_TEST_SIDDQ;