drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set

The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.

For the CMD panel usecase some of IRQ indexes depend on the selected
resources. Move setting them to the irq_enable() callback.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577529/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-3-caf5dcd125c0@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b740bbbfbf4e81dd72c7ad695c88416ad591eebd..679131f5c035f1d4235b20c73920cac12a302fe4 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1159,8 +1159,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
                phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
 
                phys->cached_mode = crtc_state->adjusted_mode;
-               if (phys->ops.atomic_mode_set)
-                       phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
        }
 }
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 8c5b0c8535729811effc73eebd3bc9be36fc5b07..7eb8bdfe6bbedbfef94f28a8958f127fa63a8f13 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -69,8 +69,6 @@ struct dpu_encoder_phys;
  * @is_master:                 Whether this phys_enc is the current master
  *                             encoder. Can be switched at enable time. Based
  *                             on split_role and current mode (CMD/VID).
- * @atomic_mode_set:           DRM Call. Set a DRM mode.
- *                             This likely caches the mode, for use at enable.
  * @enable:                    DRM Call. Enable a DRM mode.
  * @disable:                   DRM Call. Disable mode.
  * @atomic_check:              DRM Call. Atomic check new DRM state.
@@ -96,9 +94,6 @@ struct dpu_encoder_phys;
 struct dpu_encoder_phys_ops {
        void (*prepare_commit)(struct dpu_encoder_phys *encoder);
        bool (*is_master)(struct dpu_encoder_phys *encoder);
-       void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
-                       struct drm_crtc_state *crtc_state,
-                       struct drm_connector_state *conn_state);
        void (*enable)(struct dpu_encoder_phys *encoder);
        void (*disable)(struct dpu_encoder_phys *encoder);
        int (*atomic_check)(struct dpu_encoder_phys *encoder,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index de826f9745e55e782ddfc7e69f09a020317e4ffc..fc1d5736d7fcc33cdefad68e5b052b7146601c41 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -142,23 +142,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg)
        dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
 }
 
-static void dpu_encoder_phys_cmd_atomic_mode_set(
-               struct dpu_encoder_phys *phys_enc,
-               struct drm_crtc_state *crtc_state,
-               struct drm_connector_state *conn_state)
-{
-       phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
-
-       phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
-
-       if (phys_enc->has_intf_te)
-               phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr;
-       else
-               phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr;
-
-       phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
-}
-
 static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
                struct dpu_encoder_phys *phys_enc)
 {
@@ -297,6 +280,14 @@ static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc)
                                          phys_enc->hw_pp->idx - PINGPONG_0,
                                          phys_enc->vblank_refcount);
 
+       phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
+       phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
+
+       if (phys_enc->has_intf_te)
+               phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr;
+       else
+               phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr;
+
        dpu_core_irq_register_callback(phys_enc->dpu_kms,
                                       phys_enc->irq[INTR_IDX_PINGPONG],
                                       dpu_encoder_phys_cmd_pp_tx_done_irq,
@@ -327,6 +318,10 @@ static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc)
        dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]);
        dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
        dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]);
+
+       phys_enc->irq[INTR_IDX_CTL_START] = 0;
+       phys_enc->irq[INTR_IDX_PINGPONG] = 0;
+       phys_enc->irq[INTR_IDX_RDPTR] = 0;
 }
 
 static void dpu_encoder_phys_cmd_tearcheck_config(
@@ -706,7 +701,6 @@ static void dpu_encoder_phys_cmd_init_ops(
                struct dpu_encoder_phys_ops *ops)
 {
        ops->is_master = dpu_encoder_phys_cmd_is_master;
-       ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set;
        ops->enable = dpu_encoder_phys_cmd_enable;
        ops->disable = dpu_encoder_phys_cmd_disable;
        ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;
@@ -745,6 +739,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev,
 
        dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
        phys_enc->intf_mode = INTF_MODE_CMD;
+       phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
+
        cmd_enc->stream_sel = 0;
 
        if (!phys_enc->hw_intf) {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 3943d5588ddc539533983012de87ac24b388c646..2aa72b57876457b4cdbfc8a8059f4425fd590444 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -350,16 +350,6 @@ static bool dpu_encoder_phys_vid_needs_single_flush(
        return phys_enc->split_role != ENC_ROLE_SOLO;
 }
 
-static void dpu_encoder_phys_vid_atomic_mode_set(
-               struct dpu_encoder_phys *phys_enc,
-               struct drm_crtc_state *crtc_state,
-               struct drm_connector_state *conn_state)
-{
-       phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
-
-       phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
-}
-
 static int dpu_encoder_phys_vid_control_vblank_irq(
                struct dpu_encoder_phys *phys_enc,
                bool enable)
@@ -687,7 +677,6 @@ static int dpu_encoder_phys_vid_get_frame_count(
 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
 {
        ops->is_master = dpu_encoder_phys_vid_is_master;
-       ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
        ops->enable = dpu_encoder_phys_vid_enable;
        ops->disable = dpu_encoder_phys_vid_disable;
        ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
@@ -726,6 +715,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
 
        dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
        phys_enc->intf_mode = INTF_MODE_VIDEO;
+       phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
+       phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
 
        DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 60201372548487bd2341d9009cf62fe976764ff5..a0a28230fc31e299e6980a6490777cdc9768ac92 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -539,15 +539,6 @@ static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys)
                dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
 }
 
-static void dpu_encoder_phys_wb_atomic_mode_set(
-               struct dpu_encoder_phys *phys_enc,
-               struct drm_crtc_state *crtc_state,
-               struct drm_connector_state *conn_state)
-{
-
-       phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
-}
-
 static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
                struct dpu_encoder_phys *phys_enc)
 {
@@ -784,7 +775,6 @@ static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phy
 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
 {
        ops->is_master = dpu_encoder_phys_wb_is_master;
-       ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
        ops->enable = dpu_encoder_phys_wb_enable;
        ops->disable = dpu_encoder_phys_wb_disable;
        ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
@@ -831,6 +821,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
 
        dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
        phys_enc->intf_mode = INTF_MODE_WB_LINE;
+       phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
 
        atomic_set(&wb_enc->wbirq_refcount, 0);