drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2

Otherwise, without RLC reinitialization, the DPM reenablement
will fail. That affects the custom pptable uploading.

V2: setting/clearing uploading_custom_pp_table in
    smu_sys_set_pp_table()

Reported-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 69243a858dd541b1a38cfc7fd4310f60186118cb..14aecf6c6844dd39e9a6bbecee27af8d90fef30a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
        smu_table->power_play_table = smu_table->hardcode_pptable;
        smu_table->power_play_table_size = size;
 
+       /*
+        * Special hw_fini action(for Navi1x, the DPMs disablement will be
+        * skipped) may be needed for custom pptable uploading.
+        */
+       smu->uploading_custom_pp_table = true;
+
        ret = smu_reset(smu);
        if (ret)
                pr_info("smu reset failed, ret = %d\n", ret);
 
+       smu->uploading_custom_pp_table = false;
+
 failed:
        mutex_unlock(&smu->mutex);
        return ret;
@@ -1295,10 +1303,25 @@ static int smu_hw_fini(void *handle)
                return ret;
        }
 
-       ret = smu_stop_dpms(smu);
-       if (ret) {
-               pr_warn("Fail to stop Dpms!\n");
-               return ret;
+       /*
+        * For custom pptable uploading, skip the DPM features
+        * disable process on Navi1x ASICs.
+        *   - As the gfx related features are under control of
+        *     RLC on those ASICs. RLC reinitialization will be
+        *     needed to reenable them. That will cost much more
+        *     efforts.
+        *
+        *   - SMU firmware can handle the DPM reenablement
+        *     properly.
+        */
+       if (!smu->uploading_custom_pp_table ||
+           !((adev->asic_type >= CHIP_NAVI10) &&
+             (adev->asic_type <= CHIP_NAVI12))) {
+               ret = smu_stop_dpms(smu);
+               if (ret) {
+                       pr_warn("Fail to stop Dpms!\n");
+                       return ret;
+               }
        }
 
        kfree(table_context->driver_pptable);

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 999445c5c010721700adaa48a31a1ed99d782c4e..031e0c22fcc7b38e0cc5eaed54127faa1f8c154f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -390,6 +390,7 @@ struct smu_context
 
        uint32_t smc_if_version;
 
+       bool uploading_custom_pp_table;
 };
 
 struct i2c_adapter;