drm/i915: Remove chipset flush after cache flush

We always flush the chipset prior to executing with the GPU, so we can
skip the flush during ordinary domain management.

This should help mitigate some of the potential performance regressions,
but likely trivial, from doing the flush unconditionally before execbuf
introduced in commit dcd79934b0dd ("drm/i915: Unconditionally flush any
chipset buffers before execbuf")

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20161106130001.9509-1-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80775b882b4a58045716d56b6adca6509c8e62c9..91bec6065fe7dd1bdca0a92d76e1b9f74d4a595f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3403,7 +3403,7 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
 
 void i915_gem_reset(struct drm_i915_private *dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
-bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
+void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
 int __must_check i915_gem_init(struct drm_device *dev);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
 void i915_gem_init_swizzling(struct drm_device *dev);

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41e697e5dbcd781b4ea34be7bd5d390b27af952d..d2ad73d0b5b968ba74064ea6c5816928f0a16f79 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3196,23 +3196,22 @@ err_unpin:
        return ret;
 }
 
-bool
-i915_gem_clflush_object(struct drm_i915_gem_object *obj,
-                       bool force)
+void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
+                            bool force)
 {
        /* If we don't have a page list set up, then we're not pinned
         * to GPU, and we can ignore the cache flush because it'll happen
         * again at bind time.
         */
        if (!obj->mm.pages)
-               return false;
+               return;
 
        /*
         * Stolen memory is always coherent with the GPU as it is explicitly
         * marked as wc by the system, or the system is cache-coherent.
         */
        if (obj->stolen || obj->phys_handle)
-               return false;
+               return;
 
        /* If the GPU is snooping the contents of the CPU cache,
         * we do not need to manually clear the CPU cache lines.  However,
@@ -3224,14 +3223,12 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj,
         */
        if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
                obj->cache_dirty = true;
-               return false;
+               return;
        }
 
        trace_i915_gem_object_clflush(obj);
        drm_clflush_sg(obj->mm.pages);
        obj->cache_dirty = false;
-
-       return true;
 }
 
 /** Flushes the GTT write domain for the object if it's dirty. */
@@ -3277,9 +3274,7 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
        if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
                return;
 
-       if (i915_gem_clflush_object(obj, obj->pin_display))
-               i915_gem_chipset_flush(to_i915(obj->base.dev));
-
+       i915_gem_clflush_object(obj, obj->pin_display);
        intel_fb_obj_flush(obj, false, ORIGIN_CPU);
 
        obj->base.write_domain = 0;
@@ -3486,10 +3481,8 @@ out:
         * object is now coherent at its new cache level (with respect
         * to the access domain).
         */
-       if (obj->cache_dirty && cpu_write_needs_clflush(obj)) {
-               if (i915_gem_clflush_object(obj, true))
-                       i915_gem_chipset_flush(to_i915(obj->base.dev));
-       }
+       if (obj->cache_dirty && cpu_write_needs_clflush(obj))
+               i915_gem_clflush_object(obj, true);
 
        return 0;
 }