{
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       enum transcoder cpu_transcoder;
        struct drm_display_mode *mode;
        struct intel_crtc_state *pipe_config;
-       u32 htot, hsync, vtot, vsync;
        enum pipe pipe = intel_crtc->pipe;
 
        mode = kzalloc(sizeof(*mode), GFP_KERNEL);
        pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
        i9xx_crtc_clock_get(intel_crtc, pipe_config);
 
-       mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
-
-       cpu_transcoder = pipe_config->cpu_transcoder;
-       htot = I915_READ(HTOTAL(cpu_transcoder));
-       hsync = I915_READ(HSYNC(cpu_transcoder));
-       vtot = I915_READ(VTOTAL(cpu_transcoder));
-       vsync = I915_READ(VSYNC(cpu_transcoder));
+       pipe_config->base.adjusted_mode.crtc_clock =
+               pipe_config->port_clock / pipe_config->pixel_multiplier;
 
-       mode->hdisplay = (htot & 0xffff) + 1;
-       mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
-       mode->hsync_start = (hsync & 0xffff) + 1;
-       mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
-       mode->vdisplay = (vtot & 0xffff) + 1;
-       mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
-       mode->vsync_start = (vsync & 0xffff) + 1;
-       mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
+       intel_get_pipe_timings(intel_crtc, pipe_config);
 
-       drm_mode_set_name(mode);
+       intel_mode_from_pipe_config(mode, pipe_config);
 
        kfree(pipe_config);