drm/msm/a6xx: set ubwc config for A640 and A650

This is required for A640 and A650 to be able to share UBWC-compressed
images with other HW such as display, which expect this configuration.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 9f970cbc65adebddef18cbe6a6ec6c3515cee146..85a4dfde5505865ac838f704151e8f24e95e0286 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -292,6 +292,37 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
        gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0);
 }
 
+static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
+{
+       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       u32 lower_bit = 2;
+       u32 amsbc = 0;
+       u32 rgb565_predicator = 0;
+       u32 uavflagprd_inv = 0;
+
+       /* a618 is using the hw default values */
+       if (adreno_is_a618(adreno_gpu))
+               return;
+
+       if (adreno_is_a640(adreno_gpu))
+               amsbc = 1;
+
+       if (adreno_is_a650(adreno_gpu)) {
+               /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
+               lower_bit = 3;
+               amsbc = 1;
+               rgb565_predicator = 1;
+               uavflagprd_inv = 2;
+       }
+
+       gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
+               rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
+       gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
+       gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
+               uavflagprd_inv >> 4 | lower_bit << 1);
+       gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
+}
+
 static int a6xx_cp_init(struct msm_gpu *gpu)
 {
        struct msm_ringbuffer *ring = gpu->rb[0];
@@ -481,12 +512,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
        /* Select CP0 to always count cycles */
        gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
 
-       if (adreno_is_a630(adreno_gpu)) {
-               gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
-               gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
-               gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
-               gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
-       }
+       a6xx_set_ubwc_config(gpu);
 
        /* Enable fault detection */
        gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,