int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+
        sdma_v4_0_init_golden_registers(adev);
 
        r = sdma_v4_0_start(adev);
        sdma_v4_0_ctx_switch_enable(adev, false);
        sdma_v4_0_enable(adev, false);
 
+       if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
+
        return 0;
 }
 
 
        .smus_notify_pwe = smu10_smus_notify_pwe,
        .display_clock_voltage_request = smu10_display_clock_voltage_request,
        .powergate_gfx = smu10_gfx_off_control,
+       .powergate_sdma = smu10_powergate_sdma,
 };
 
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
 
        return 0;
 }
 
-/* sdma is disabled by default in vbios, need to re-enable in driver */
-static void smu10_smc_enable_sdma(struct pp_hwmgr *hwmgr)
-{
-       smu10_send_msg_to_smc(hwmgr,
-                       PPSMC_MSG_PowerUpSdma);
-}
-
-static void smu10_smc_disable_sdma(struct pp_hwmgr *hwmgr)
-{
-       smu10_send_msg_to_smc(hwmgr,
-                       PPSMC_MSG_PowerDownSdma);
-}
-
 /* vcn is disabled by default in vbios, need to re-enable in driver */
 static void smu10_smc_enable_vcn(struct pp_hwmgr *hwmgr)
 {
                        (struct smu10_smumgr *)(hwmgr->smu_backend);
 
        if (priv) {
-               smu10_smc_disable_sdma(hwmgr);
                smu10_smc_disable_vcn(hwmgr);
                amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
                                        &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
 
        if (smu10_verify_smc_interface(hwmgr))
                return -EINVAL;
-       smu10_smc_enable_sdma(hwmgr);
        smu10_smc_enable_vcn(hwmgr);
        return 0;
 }