SAVE_ITEM(S5P_SROM_BC3),
 };
 
-static struct sleep_save exynos4_l2cc_save[] = {
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
-       SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
-};
 
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
        u32 tmp;
 
        s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
-       s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
        s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
        s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
 
        scu_enable(S5P_VA_SCU);
 
-#ifdef CONFIG_CACHE_L2X0
-       s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-       outer_inv_all();
-       /* enable L2X0*/
-       writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
-#endif
-
 early_wakeup:
        return;
 }