drm/amdgpu: move cache window setup after power and clock resume

To make register read/write reliable

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index b82c92084b6f413731d73e230f84b97d31c5b3cc..ca4265bc10b9969102947527d9b4f3a786dacdfc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -600,12 +600,12 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
        /* disable byte swapping */
        lmi_swap_cntl = 0;
 
-       vcn_v1_0_mc_resume(adev);
-
        vcn_1_0_disable_static_power_gating(adev);
        /* disable clock gating */
        vcn_v1_0_disable_clock_gating(adev);
 
+       vcn_v1_0_mc_resume(adev);
+
        /* disable interupt */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
                        ~UVD_MASTINT_EN__VCPU_EN_MASK);