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iommu/arm-smmu: Add CB prefix to register bitfields
authorRob Clark <robdclark@chromium.org>
Mon, 1 Jul 2024 16:20:10 +0000 (09:20 -0700)
committerWill Deacon <will@kernel.org>
Tue, 2 Jul 2024 17:02:00 +0000 (18:02 +0100)
For consistency, add the "CB" prefix to the bitfield defines for context
registers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Pranjal Shrivastava <praan@google.com>
Link: https://lore.kernel.org/r/20240701162025.375134-2-robdclark@gmail.com
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c patch | blob | history
drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c patch | blob | history
drivers/iommu/arm/arm-smmu/arm-smmu.c patch | blob | history
drivers/iommu/arm/arm-smmu/arm-smmu.h patch | blob | history
drivers/iommu/arm/arm-smmu/qcom_iommu.c patch | blob | history

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
index 957d988b6d832f55a7bbe31adb0b15e89296489d..4b2994b6126df5e2b9bf73b42d204d1660ccaa81 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
@@ -200,7 +200,7 @@ static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
        void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
 
        fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
-       if (!(fsr & ARM_SMMU_FSR_FAULT))
+       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
                return IRQ_NONE;
 
        fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 552199cbd9e25dfba1f9db2a9799ed13dfc06ca2..e4ee78fb6a663bdb964e6af66ec91d6b928abf66 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -141,7 +141,7 @@ static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_doma
        writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
 
        fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
-       if ((fsr & ARM_SMMU_FSR_FAULT) && (fsr & ARM_SMMU_FSR_SS)) {
+       if ((fsr & ARM_SMMU_CB_FSR_FAULT) && (fsr & ARM_SMMU_CB_FSR_SS)) {
                u32 sctlr_orig, sctlr;
 
                /*
@@ -298,7 +298,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
 
        fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
-       if (fsr & ARM_SMMU_FSR_FAULT) {
+       if (fsr & ARM_SMMU_CB_FSR_FAULT) {
                /* Clear pending interrupts */
                arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
 
@@ -306,7 +306,7 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
                 * TBU halt takes care of resuming any stalled transcation.
                 * Kept it here for completeness sake.
                 */
-               if (fsr & ARM_SMMU_FSR_SS)
+               if (fsr & ARM_SMMU_CB_FSR_SS)
                        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
                                          ARM_SMMU_RESUME_TERMINATE);
        }
@@ -320,11 +320,11 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
                        phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid);
 
                        fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
-                       if (fsr & ARM_SMMU_FSR_FAULT) {
+                       if (fsr & ARM_SMMU_CB_FSR_FAULT) {
                                /* Clear pending interrupts */
                                arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
 
-                               if (fsr & ARM_SMMU_FSR_SS)
+                               if (fsr & ARM_SMMU_CB_FSR_SS)
                                        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
                                                          ARM_SMMU_RESUME_TERMINATE);
                        }
@@ -394,7 +394,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
                                      DEFAULT_RATELIMIT_BURST);
 
        fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
-       if (!(fsr & ARM_SMMU_FSR_FAULT))
+       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
                return IRQ_NONE;
 
        fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
@@ -403,7 +403,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
 
        if (list_empty(&tbu_list)) {
                ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
-                                        fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+                                        fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
 
                if (ret == -ENOSYS)
                        dev_err_ratelimited(smmu->dev,
@@ -417,7 +417,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
        phys_soft = ops->iova_to_phys(ops, iova);
 
        tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
-                                fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+                                fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
        if (!tmp || tmp == -EBUSY) {
                dev_dbg(smmu->dev,
                        "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
@@ -481,7 +481,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
                arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
 
                /* Retry or terminate any stalled transactions */
-               if (fsr & ARM_SMMU_FSR_SS)
+               if (fsr & ARM_SMMU_CB_FSR_SS)
                        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
        }
 
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 87c81f75cf844bd58492091bede23a1f2cb867ee..23cf91ac409bc35e0539d7dba3bde1f51f7ec457 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -415,7 +415,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
        int ret;
 
        fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
-       if (!(fsr & ARM_SMMU_FSR_FAULT))
+       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
                return IRQ_NONE;
 
        fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
@@ -423,7 +423,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
        cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
 
        ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
-               fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+               fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
 
        if (ret == -ENOSYS)
                dev_err_ratelimited(smmu->dev,
@@ -1306,7 +1306,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
                arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
 
        reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR;
-       if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_ATSR_ACTIVE),
+       if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_CB_ATSR_ACTIVE),
                                      5, 50)) {
                spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
                dev_err(dev,
@@ -1642,7 +1642,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
        /* Make sure all context banks are disabled and clear CB_FSR  */
        for (i = 0; i < smmu->num_context_banks; ++i) {
                arm_smmu_write_context_bank(smmu, i);
-               arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
+               arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
        }
 
        /* Invalidate the TLB, just in case */
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 4765c6945c344dec36d250fde94d9134c0fe194a..b04a00126a12526006dad3f9daebdc51c47c2452 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -196,34 +196,34 @@ enum arm_smmu_cbar_type {
 #define ARM_SMMU_CB_PAR_F              BIT(0)
 
 #define ARM_SMMU_CB_FSR                        0x58
-#define ARM_SMMU_FSR_MULTI             BIT(31)
-#define ARM_SMMU_FSR_SS                        BIT(30)
-#define ARM_SMMU_FSR_UUT               BIT(8)
-#define ARM_SMMU_FSR_ASF               BIT(7)
-#define ARM_SMMU_FSR_TLBLKF            BIT(6)
-#define ARM_SMMU_FSR_TLBMCF            BIT(5)
-#define ARM_SMMU_FSR_EF                        BIT(4)
-#define ARM_SMMU_FSR_PF                        BIT(3)
-#define ARM_SMMU_FSR_AFF               BIT(2)
-#define ARM_SMMU_FSR_TF                        BIT(1)
-
-#define ARM_SMMU_FSR_IGN               (ARM_SMMU_FSR_AFF |             \
-                                        ARM_SMMU_FSR_ASF |             \
-                                        ARM_SMMU_FSR_TLBMCF |          \
-                                        ARM_SMMU_FSR_TLBLKF)
-
-#define ARM_SMMU_FSR_FAULT             (ARM_SMMU_FSR_MULTI |           \
-                                        ARM_SMMU_FSR_SS |              \
-                                        ARM_SMMU_FSR_UUT |             \
-                                        ARM_SMMU_FSR_EF |              \
-                                        ARM_SMMU_FSR_PF |              \
-                                        ARM_SMMU_FSR_TF |              \
-                                        ARM_SMMU_FSR_IGN)
+#define ARM_SMMU_CB_FSR_MULTI          BIT(31)
+#define ARM_SMMU_CB_FSR_SS             BIT(30)
+#define ARM_SMMU_CB_FSR_UUT            BIT(8)
+#define ARM_SMMU_CB_FSR_ASF            BIT(7)
+#define ARM_SMMU_CB_FSR_TLBLKF         BIT(6)
+#define ARM_SMMU_CB_FSR_TLBMCF         BIT(5)
+#define ARM_SMMU_CB_FSR_EF             BIT(4)
+#define ARM_SMMU_CB_FSR_PF             BIT(3)
+#define ARM_SMMU_CB_FSR_AFF            BIT(2)
+#define ARM_SMMU_CB_FSR_TF             BIT(1)
+
+#define ARM_SMMU_CB_FSR_IGN            (ARM_SMMU_CB_FSR_AFF |          \
+                                        ARM_SMMU_CB_FSR_ASF |          \
+                                        ARM_SMMU_CB_FSR_TLBMCF |       \
+                                        ARM_SMMU_CB_FSR_TLBLKF)
+
+#define ARM_SMMU_CB_FSR_FAULT          (ARM_SMMU_CB_FSR_MULTI |        \
+                                        ARM_SMMU_CB_FSR_SS |           \
+                                        ARM_SMMU_CB_FSR_UUT |          \
+                                        ARM_SMMU_CB_FSR_EF |           \
+                                        ARM_SMMU_CB_FSR_PF |           \
+                                        ARM_SMMU_CB_FSR_TF |           \
+                                        ARM_SMMU_CB_FSR_IGN)
 
 #define ARM_SMMU_CB_FAR                        0x60
 
 #define ARM_SMMU_CB_FSYNR0             0x68
-#define ARM_SMMU_FSYNR0_WNR            BIT(4)
+#define ARM_SMMU_CB_FSYNR0_WNR         BIT(4)
 
 #define ARM_SMMU_CB_FSYNR1             0x6c
 
@@ -237,7 +237,7 @@ enum arm_smmu_cbar_type {
 #define ARM_SMMU_CB_ATS1PR             0x800
 
 #define ARM_SMMU_CB_ATSR               0x8f0
-#define ARM_SMMU_ATSR_ACTIVE           BIT(0)
+#define ARM_SMMU_CB_ATSR_ACTIVE                BIT(0)
 
 #define ARM_SMMU_RESUME_TERMINATE      BIT(0)
 
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index e079bb7a993e29e869260683ca8c961b9b46e516..b98a7a598b89739daedaa218b0f63e0ff707ec77 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -194,7 +194,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
 
        fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
 
-       if (!(fsr & ARM_SMMU_FSR_FAULT))
+       if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
                return IRQ_NONE;
 
        fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
@@ -274,7 +274,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 
                /* Clear context bank fault address fault status registers */
                iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
-               iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
+               iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
 
                /* TTBRs */
                iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
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