Merge branch kvm-arm64/nv-6.8-prefix into kvmarm-master/next

* kvm-arm64/nv-6.8-prefix:
  : .
  : Nested Virtualization support update, focussing on the
  : NV2 support (VNCR mapping and such).
  : .
  KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg()
  KVM: arm64: nv: Map VNCR-capable registers to a separate page
  KVM: arm64: nv: Add EL2_REG_VNCR()/EL2_REG_REDIR() sysreg helpers
  KVM: arm64: Introduce a bad_trap() primitive for unexpected trap handling
  KVM: arm64: nv: Add include containing the VNCR_EL2 offsets
  KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers
  KVM: arm64: nv: Drop EL12 register traps that are redirected to VNCR
  KVM: arm64: nv: Compute NV view of idregs as a one-off
  KVM: arm64: nv: Hoist vcpu_has_nv() into is_hyp_ctxt()
  arm64: cpufeatures: Restrict NV support to FEAT_NV2

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --cc arch/arm64/include/asm/kvm_emulate.h
Simple merge

diff --cc arch/arm64/include/asm/kvm_host.h
index ba14648e2de25945806bded615d6c1e61d7b015e,f17fb7c42973dabfc51e88b5fecf26065accd438..ed4c6e8d3417c9bcad71f545103e9d64c10a3a30
--- 1/arch/arm64/include/asm/kvm_host.h
--- 2/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@@ -449,6 -422,54 +422,55 @@@ enum vcpu_sysreg 
        CNTHV_CTL_EL2,
        CNTHV_CVAL_EL2,
  
+       __VNCR_START__, /* Any VNCR-capable reg goes after this point */
+ 
+       VNCR(SCTLR_EL1),/* System Control Register */
+       VNCR(ACTLR_EL1),/* Auxiliary Control Register */
+       VNCR(CPACR_EL1),/* Coprocessor Access Control */
+       VNCR(ZCR_EL1),  /* SVE Control */
+       VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
+       VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
+       VNCR(TCR_EL1),  /* Translation Control Register */
+       VNCR(TCR2_EL1), /* Extended Translation Control Register */
+       VNCR(ESR_EL1),  /* Exception Syndrome Register */
+       VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
+       VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
+       VNCR(FAR_EL1),  /* Fault Address Register */
+       VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */
+       VNCR(VBAR_EL1), /* Vector Base Address Register */
+       VNCR(CONTEXTIDR_EL1),   /* Context ID Register */
+       VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
+       VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
+       VNCR(ELR_EL1),
+       VNCR(SP_EL1),
+       VNCR(SPSR_EL1),
+       VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */
+       VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
+       VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
+       VNCR(HCR_EL2),  /* Hypervisor Configuration Register */
+       VNCR(HSTR_EL2), /* Hypervisor System Trap Register */
+       VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
+       VNCR(VTCR_EL2), /* Virtualization Translation Control Register */
+       VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
+       VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */
+ 
+       /* Permission Indirection Extension registers */
+       VNCR(PIR_EL1),   /* Permission Indirection Register 1 (EL1) */
+       VNCR(PIRE0_EL1), /*  Permission Indirection Register 0 (EL1) */
+ 
+       VNCR(HFGRTR_EL2),
+       VNCR(HFGWTR_EL2),
+       VNCR(HFGITR_EL2),
+       VNCR(HDFGRTR_EL2),
+       VNCR(HDFGWTR_EL2),
++      VNCR(HAFGRTR_EL2),
+ 
+       VNCR(CNTVOFF_EL2),
+       VNCR(CNTV_CVAL_EL0),
+       VNCR(CNTV_CTL_EL0),
+       VNCR(CNTP_CVAL_EL0),
+       VNCR(CNTP_CTL_EL0),
+ 
        NR_SYS_REGS     /* Nothing after this line! */
  };
  

diff --cc arch/arm64/kernel/cpufeature.c
Simple merge

diff --cc arch/arm64/kvm/arm.c
Simple merge

diff --cc arch/arm64/kvm/sys_regs.c
index 8bb297a2df3882db4e8623b9dbd8e707637f28c9,3198542dcded6227baf5312097f76b25e69c1c6d..b4d3486d66ffd6fbdb84f95005a55e2cdad50a9c
--- 1/arch/arm64/kvm/sys_regs.c
--- 2/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@@ -2526,15 -2679,14 +2679,15 @@@ static const struct sys_reg_desc sys_re
        EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
        EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
        EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
-       EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
-       EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
+       EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
+       EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
  
        { SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },
-       EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
-       EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
-       EL2_REG(HAFGRTR_EL2, access_rw, reset_val, 0),
-       EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
-       EL2_REG(ELR_EL2, access_rw, reset_val, 0),
+       EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0),
+       EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0),
++      EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0),
+       EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
+       EL2_REG_REDIR(ELR_EL2, reset_val, 0),
        { SYS_DESC(SYS_SP_EL1), access_sp_el1},
  
        /* AArch32 SPSR_* are RES0 if trapped from a NV guest */