drm/amdgpu: switch to select_se_sh wrapper for gfx v9_0

To allow invoking ip specific callbacks

Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 81e3b528bbc9bc2d96416e50d5b6c93ffe707659..e92b93557c13fa382a6ee4d66d4e43ef96b842d8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -787,7 +787,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
        for (se_idx = 0; se_idx < se_cnt; se_idx++) {
                for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {
 
-                       gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);
+                       amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);
                        queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);
 
                        /*
@@ -820,7 +820,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
                }
        }
 
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        soc15_grbm_select(adev, 0, 0, 0, 0);
        unlock_spi_csq_mutexes(adev);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c80623c35b52ae99f6ca7ef9de1c9b3d5049280d..ab30c18decfbe8dd5098ee06e1455217f060f4b4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1564,7 +1564,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
                        mask = 1;
                        cu_bitmap = 0;
                        counter = 0;
-                       gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
+                       amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff);
 
                        for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
                                if (cu_info->bitmap[i][j] & mask) {
@@ -1583,7 +1583,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
                        cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
                }
        }
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        mutex_unlock(&adev->grbm_idx_mutex);
 }
 
@@ -1605,7 +1605,7 @@ static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 
        mutex_lock(&adev->grbm_idx_mutex);
        /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 
        /* set mmRLC_LB_PARAMS = 0x003F_1006 */
@@ -1654,7 +1654,7 @@ static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
 
        mutex_lock(&adev->grbm_idx_mutex);
        /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 
        /* set mmRLC_LB_PARAMS = 0x003F_1006 */
@@ -2322,13 +2322,13 @@ static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
-                       gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
+                       amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff);
                        data = gfx_v9_0_get_rb_active_bitmap(adev);
                        active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
                                               rb_bitmap_width_per_sh);
                }
        }
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        mutex_unlock(&adev->grbm_idx_mutex);
 
        adev->gfx.config.backend_enable_mask = active_rbs;
@@ -2465,14 +2465,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
-                       gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
+                       amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff);
                        for (k = 0; k < adev->usec_timeout; k++) {
                                if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
                                        break;
                                udelay(1);
                        }
                        if (k == adev->usec_timeout) {
-                               gfx_v9_0_select_se_sh(adev, 0xffffffff,
+                               amdgpu_gfx_select_se_sh(adev, 0xffffffff,
                                                      0xffffffff, 0xffffffff);
                                mutex_unlock(&adev->grbm_idx_mutex);
                                DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
@@ -2481,7 +2481,7 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
                        }
                }
        }
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        mutex_unlock(&adev->grbm_idx_mutex);
 
        mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
@@ -6482,7 +6482,7 @@ static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev)
        for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
                for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
                        for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
-                               gfx_v9_0_select_se_sh(adev, j, 0x0, k);
+                               amdgpu_gfx_select_se_sh(adev, j, 0x0, k);
                                RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
                        }
                }
@@ -6544,7 +6544,7 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
        for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
                for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
                        for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
-                               gfx_v9_0_select_se_sh(adev, j, 0, k);
+                               amdgpu_gfx_select_se_sh(adev, j, 0, k);
                                reg_value =
                                        RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
                                if (reg_value)
@@ -6559,7 +6559,7 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
        err_data->ce_count += sec_count;
        err_data->ue_count += ded_count;
 
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        mutex_unlock(&adev->grbm_idx_mutex);
 
        gfx_v9_0_query_utc_edc_status(adev, err_data);
@@ -6963,7 +6963,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
                        mask = 1;
                        ao_bitmap = 0;
                        counter = 0;
-                       gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
+                       amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff);
                        gfx_v9_0_set_user_cu_inactive_bitmap(
                                adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
                        bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
@@ -6996,7 +6996,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
                        cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
                }
        }
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+       amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
        mutex_unlock(&adev->grbm_idx_mutex);
 
        cu_info->number = active_cu_number;