PCI: dwc: Support 16-lane operation

Some hosts support 16 lanes of PCIe. Make num-lanes accept that number.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250926-topic-pcie_16ln-v1-1-c249acc18790@oss.qualcomm.com

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 89aad5a08928cc29870ab258d33bee9ff8f83143..42e4d8efba812ca73556bab4b1827da56d63fad9 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -841,6 +841,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
        case 8:
                plc |= PORT_LINK_MODE_8_LANES;
                break;
+       case 16:
+               plc |= PORT_LINK_MODE_16_LANES;
+               break;
        default:
                dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
                return;

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00f52d472dcdd794013a865ad6c4c7cc251edb48..ed0cbb038038768acecaf587dc32a39963af69c5 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -90,6 +90,7 @@
 #define PORT_LINK_MODE_2_LANES         PORT_LINK_MODE(0x3)
 #define PORT_LINK_MODE_4_LANES         PORT_LINK_MODE(0x7)
 #define PORT_LINK_MODE_8_LANES         PORT_LINK_MODE(0xf)
+#define PORT_LINK_MODE_16_LANES                PORT_LINK_MODE(0x1f)
 
 #define PCIE_PORT_LANE_SKEW            0x714
 #define PORT_LANE_SKEW_INSERT_MASK     GENMASK(23, 0)