drm/amd/display: Clean up indentation in dce120_tg_set_blank()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 1e2843e5d97e86fc9a56454cc41f301e3b9a8e99..c208196864adb275c2e59fce10ca57836ae2d4e5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_generator *tg,
                CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
                CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
 
-       if (enable_blanking) {
-               CRTC_REG_SET(
-                       CRTC0_CRTC_BLANK_CONTROL,
-                       CRTC_BLANK_DATA_EN, 1);
-
-       } else
-               dm_write_reg_soc15(
-                       tg->ctx,
-                       mmCRTC0_CRTC_BLANK_CONTROL,
-                       tg110->offsets.crtc,
-                       0);
+       if (enable_blanking)
+               CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
+       else
+               dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
+                       tg110->offsets.crtc, 0);
 }
 
 bool dce120_tg_validate_timing(struct timing_generator *tg,