arm64: dts: exynos: Add internal eMMC support to jackpotlte

Add the nodes relevant to provide clocks for Exynos7885 eMMC and to
support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8
(2018) (jackpotlte), and all other known devices using the Exynos7885
SoC.

Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20220601233743.56317-6-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
index 4cf9aa25f6180368e280d9f489a8297da37565e0..5db9a81ac7bb54881e75a18aa8696104b7e1e049 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
@@ -60,6 +60,26 @@
        };
 };
 
+&mmc_0 {
+       status = "okay";
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       cap-mmc-highspeed;
+       non-removable;
+       mmc-hs400-enhanced-strobe;
+       card-detect-delay = <200>;
+       clock-frequency = <800000000>;
+       bus-width = <8>;
+       samsung,dw-mshc-ciu-div = <3>;
+       samsung,dw-mshc-sdr-timing = <0 4>;
+       samsung,dw-mshc-ddr-timing = <2 4>;
+       samsung,dw-mshc-hs400-timing = <0 2>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs
+                    &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+};
+
 &oscclk {
        clock-frequency = <26000000>;
 };

diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
index 3170661f5b67258867e32aefca3c79276c225347..40be504b307885e5116974a150b6ac1697daefb2 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
@@ -240,6 +240,25 @@
                        clock-names = "oscclk";
                };
 
+               cmu_fsys: clock-controller@13400000 {
+                       compatible = "samsung,exynos7885-cmu-fsys";
+                       reg = <0x13400000 0x8000>;
+                       #clock-cells = <1>;
+
+                       clocks = <&oscclk>,
+                                <&cmu_top CLK_DOUT_FSYS_BUS>,
+                                <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
+                                <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
+                                <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
+                                <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
+                       clock-names = "oscclk",
+                                     "dout_fsys_bus",
+                                     "dout_fsys_mmc_card",
+                                     "dout_fsys_mmc_embd",
+                                     "dout_fsys_mmc_sdio",
+                                     "dout_fsys_usb30drd";
+               };
+
                pinctrl_alive: pinctrl@11cb0000 {
                        compatible = "samsung,exynos7885-pinctrl";
                        reg = <0x11cb0000 0x1000>;
@@ -274,6 +293,19 @@
                        reg = <0x11c80000 0x10000>;
                };
 
+               mmc_0: mmc@13500000 {
+                       compatible = "samsung,exynos7-dw-mshc-smu";
+                       reg = <0x13500000 0x2000>;
+                       interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
+                                <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
+                       clock-names = "biu", "ciu";
+                       fifo-depth = <0x40>;
+                       status = "disabled";
+               };
+
                serial_0: serial@13800000 {
                        compatible = "samsung,exynos5433-uart";
                        reg = <0x13800000 0x100>;