drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid

Enable this only for Sienna Cichild
since only Navi12 and Sienna Cichlid support SRIOV

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f70827af618e8869c8c541f6ee4e33240c1c19eb..29951c5c04ecf50584102c86d9273cad3f5420a3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9213,7 +9213,6 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_NAVI10:
        case CHIP_NAVI14:
-       case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
        case CHIP_VANGOGH:
        case CHIP_DIMGREY_CAVEFISH:
@@ -9221,6 +9220,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
                break;
        case CHIP_NAVI12:
+       case CHIP_SIENNA_CICHLID:
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
                break;
        default: