drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32

[WHY?]
Data return times when using lowest memclk can be <= 60us, which can cause
underflow on high bandwidth displays with a workload.

[HOW?]
Enforce a minimum prefetch time during validation for low memclk modes.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 737b221ca68900bf234fa79a069d0889b5672f79..0598465fd1a1b597eb174d882f5874a1236f98b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -853,6 +853,7 @@ struct dc_debug_options {
        bool enable_dp_dig_pixel_rate_div_policy;
        enum lttpr_mode lttpr_mode_override;
        unsigned int dsc_delay_factor_wa_x1000;
+       unsigned int min_prefetch_in_strobe_ns;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index a88dd7b3d1c10e01774301b74076ecc413634881..d1598e3131f66d861099a6e29ad0e5318f1c731b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -724,6 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .enable_dp_dig_pixel_rate_div_policy = 1,
        .allow_sw_cursor_fallback = false,
        .alloc_extra_way_for_cursor = true,
+       .min_prefetch_in_strobe_ns = 60000, // 60us
 };
 
 static const struct dc_debug_options debug_defaults_diags = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 61087f2385a96ccc351bbad7e107b8d6525f31e1..6292ac515d1a448b8b492cd3fe6bc6081cfcb3b3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -722,6 +722,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .enable_dp_dig_pixel_rate_div_policy = 1,
        .allow_sw_cursor_fallback = false,
        .alloc_extra_way_for_cursor = true,
+       .min_prefetch_in_strobe_ns = 60000, // 60us
 };
 
 static const struct dc_debug_options debug_defaults_diags = {

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index f37c9a6b3b7e084d3f2e6ab2ac1df6127c5f57d1..659323ebd79d846de075e0f00960c6a9316cac9f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2364,6 +2364,8 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
        /* DML DSC delay factor workaround */
        dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
 
+       dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
+
        /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
        dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
        dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index ae6e6abc620b117139d6faf308e93d3f76a9693e..244fd15d24b433075dbbf7948765f1ad2ec23547 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -786,6 +786,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
                                        v->SwathHeightY[k],
                                        v->SwathHeightC[k],
                                        TWait,
+                                       v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
+                                                       mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
                                        /* Output */
                                        &v->DSTXAfterScaler[k],
                                        &v->DSTYAfterScaler[k],
@@ -3245,6 +3247,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
                                                        v->swath_width_chroma_ub_this_state[k],
                                                        v->SwathHeightYThisState[k],
                                                        v->SwathHeightCThisState[k], v->TWait,
+                                                       v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
+                                                                       mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
 
                                                        /* Output */
                                                        &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
index c62e0991358b32ed66fb457cebfbad64964fa09f..f82e14cd9d8aaa59038d5d8eaa1afb230d07c5c5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
@@ -49,6 +49,9 @@
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0xffffffff
 
+#define MEM_STROBE_FREQ_MHZ 1600
+#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
+
 struct display_mode_lib;
 
 void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index ab9217732a17f5d8f7ec549e4e4d70910be65327..635fc54338fa2072bb609918d0421156e74e5060 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3417,6 +3417,7 @@ bool dml32_CalculatePrefetchSchedule(
                unsigned int SwathHeightY,
                unsigned int SwathHeightC,
                double TWait,
+               double TPreReq,
                /* Output */
                double   *DSTXAfterScaler,
                double   *DSTYAfterScaler,
@@ -3474,6 +3475,7 @@ bool dml32_CalculatePrefetchSchedule(
        double  min_Lsw;
        double  Tsw_est1 = 0;
        double  Tsw_est3 = 0;
+       double  TPreMargin = 0;
 
        if (v->GPUVMEnable == true && v->HostVMEnable == true)
                HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
@@ -3699,6 +3701,8 @@ bool dml32_CalculatePrefetchSchedule(
 
        dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
        Tpre_rounded = dst_y_prefetch_equ * LineTime;
+
+       TPreMargin = Tpre_rounded - TPreReq;
 #ifdef __DML_VBA_DEBUG__
        dml_print("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, dst_y_prefetch_equ);
        dml_print("DML::%s: LineTime: %f\n", __func__, LineTime);
@@ -3726,7 +3730,7 @@ bool dml32_CalculatePrefetchSchedule(
        *VRatioPrefetchY = 0;
        *VRatioPrefetchC = 0;
        *RequiredPrefetchPixDataBWLuma = 0;
-       if (dst_y_prefetch_equ > 1) {
+       if (dst_y_prefetch_equ > 1 && TPreMargin > 0.0) {
                double PrefetchBandwidth1;
                double PrefetchBandwidth2;
                double PrefetchBandwidth3;
@@ -3872,7 +3876,11 @@ bool dml32_CalculatePrefetchSchedule(
                }
 
                if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
-                       *DestinationLinesForPrefetch = dst_y_prefetch_oto;
+                       if (dst_y_prefetch_oto * LineTime < TPreReq) {
+                               *DestinationLinesForPrefetch = dst_y_prefetch_equ;
+                       } else {
+                               *DestinationLinesForPrefetch = dst_y_prefetch_oto;
+                       }
                        TimeForFetchingMetaPTE = Tvm_oto;
                        TimeForFetchingRowInVBlank = Tr0_oto;
                        *PrefetchBandwidth = prefetch_bw_oto;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index fdccaa93eb2eff4edfbd7069003392e157fa83f8..3989c2a28faec6680392c9c4a56575a00e0be10f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -743,6 +743,7 @@ bool dml32_CalculatePrefetchSchedule(
                unsigned int SwathHeightY,
                unsigned int SwathHeightC,
                double TWait,
+               double TPreReq,
                /* Output */
                double   *DSTXAfterScaler,
                double   *DSTYAfterScaler,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index ec0486efab147e33d61e8b02e4ff37c1f4509479..432b4ecd01a710c7b14eb8ad7a946479631538f7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -544,6 +544,8 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
        /* DML DSC delay factor workaround */
        dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
 
+       dcn3_21_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
+
        /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
        dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
        dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index d7be01ac07514cde43721ec4307d2c75c0f10612..64d602e6412f16ee288c23c33e4e14bc7983a1aa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -367,6 +367,7 @@ struct _vcs_dpi_ip_params_st {
 
        /* DM workarounds */
        double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix
+       double min_prefetch_in_strobe_us;
 };
 
 struct _vcs_dpi_display_xfc_params_st {