iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used

The HW supports this, use the S1DSS bits to configure the behavior
of SSID=0 which is the RID's translation.

If SSID's are currently being used in the CD table then just update the
S1DSS bits in the STE, remove the master_domain and leave ATS alone.

For iommufd the driver design has a small problem that all the unused CD
table entries are set with V=0 which will generate an event if VFIO
userspace tries to use the CD entry. This patch extends this problem to
include the RID as well if PASID is being used.

For BLOCKED with used PASIDs the
F_STREAM_DISABLED (STRTAB_STE_1_S1DSS_TERMINATE) event is generated on
untagged traffic and a substream CD table entry with V=0 (removed pasid)
will generate C_BAD_CD. Arguably there is no advantage to using S1DSS over
the CD entry 0 with V=0.

As we don't yet support PASID in iommufd this is a problem to resolve
later, possibly by using EPD0 for unused CD table entries instead of V=0,
and not using S1DSS for BLOCKED.

Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/11-v9-5cd718286059+79186-smmuv3_newapi_p2b_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
index a460b71f58578959296badc6d09416edb92cfcf1..d7e022bb9df530702ae36d1ac4ec5d997d31b7eb 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
@@ -164,7 +164,7 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_smmu_ste *ste,
                .smmu = &smmu,
        };
 
-       arm_smmu_make_cdtable_ste(ste, &master, true);
+       arm_smmu_make_cdtable_ste(ste, &master, true, STRTAB_STE_1_S1DSS_SSID0);
 }
 
 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 148690f5b6242c8d0f1ecd2c16e01c1e478ef36f..391deb8991707174b4c3b6eb050bdf2375e7bbf0 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -991,6 +991,14 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits)
                                    STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW |
                                    STRTAB_STE_1_EATS);
                used_bits[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID);
+
+               /*
+                * See 13.5 Summary of attribute/permission configuration fields
+                * for the SHCFG behavior.
+                */
+               if (FIELD_GET(STRTAB_STE_1_S1DSS, le64_to_cpu(ent[1])) ==
+                   STRTAB_STE_1_S1DSS_BYPASS)
+                       used_bits[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG);
        }
 
        /* S2 translates */
@@ -1531,7 +1539,8 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_bypass_ste);
 
 VISIBLE_IF_KUNIT
 void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target,
-                              struct arm_smmu_master *master, bool ats_enabled)
+                              struct arm_smmu_master *master, bool ats_enabled,
+                              unsigned int s1dss)
 {
        struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table;
        struct arm_smmu_device *smmu = master->smmu;
@@ -1545,7 +1554,7 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target,
                FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax));
 
        target->data[1] = cpu_to_le64(
-               FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |
+               FIELD_PREP(STRTAB_STE_1_S1DSS, s1dss) |
                FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
                FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
                FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
@@ -1556,6 +1565,11 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target,
                FIELD_PREP(STRTAB_STE_1_EATS,
                           ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0));
 
+       if ((smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) &&
+           s1dss == STRTAB_STE_1_S1DSS_BYPASS)
+               target->data[1] |= cpu_to_le64(FIELD_PREP(
+                       STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING));
+
        if (smmu->features & ARM_SMMU_FEAT_E2H) {
                /*
                 * To support BTM the streamworld needs to match the
@@ -2579,6 +2593,7 @@ struct arm_smmu_attach_state {
        /* Inputs */
        struct iommu_domain *old_domain;
        struct arm_smmu_master *master;
+       bool cd_needs_ats;
        ioasid_t ssid;
        /* Resulting state */
        bool ats_enabled;
@@ -2620,7 +2635,7 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state,
         */
        lockdep_assert_held(&arm_smmu_asid_lock);
 
-       if (smmu_domain) {
+       if (smmu_domain || state->cd_needs_ats) {
                /*
                 * The SMMU does not support enabling ATS with bypass/abort.
                 * When the STE is in bypass (STE.Config[2:0] == 0b100), ATS
@@ -2632,7 +2647,9 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state,
                 * tables.
                 */
                state->ats_enabled = arm_smmu_ats_supported(master);
+       }
 
+       if (smmu_domain) {
                master_domain = kzalloc(sizeof(*master_domain), GFP_KERNEL);
                if (!master_domain)
                        return -ENOMEM;
@@ -2760,7 +2777,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
                arm_smmu_make_s1_cd(&target_cd, master, smmu_domain);
                arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, cdptr,
                                        &target_cd);
-               arm_smmu_make_cdtable_ste(&target, master, state.ats_enabled);
+               arm_smmu_make_cdtable_ste(&target, master, state.ats_enabled,
+                                         STRTAB_STE_1_S1DSS_SSID0);
                arm_smmu_install_ste_for_dev(master, &target);
                break;
        }
@@ -2834,8 +2852,10 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid,
        mutex_unlock(&arm_smmu_asid_lock);
 }
 
-static int arm_smmu_attach_dev_ste(struct iommu_domain *domain,
-                                  struct device *dev, struct arm_smmu_ste *ste)
+static void arm_smmu_attach_dev_ste(struct iommu_domain *domain,
+                                   struct device *dev,
+                                   struct arm_smmu_ste *ste,
+                                   unsigned int s1dss)
 {
        struct arm_smmu_master *master = dev_iommu_priv_get(dev);
        struct arm_smmu_attach_state state = {
@@ -2844,16 +2864,28 @@ static int arm_smmu_attach_dev_ste(struct iommu_domain *domain,
                .ssid = IOMMU_NO_PASID,
        };
 
-       if (arm_smmu_ssids_in_use(&master->cd_table))
-               return -EBUSY;
-
        /*
         * Do not allow any ASID to be changed while are working on the STE,
         * otherwise we could miss invalidations.
         */
        mutex_lock(&arm_smmu_asid_lock);
 
-       arm_smmu_attach_prepare(&state, domain);
+       /*
+        * If the CD table is not in use we can use the provided STE, otherwise
+        * we use a cdtable STE with the provided S1DSS.
+        */
+       if (arm_smmu_ssids_in_use(&master->cd_table)) {
+               /*
+                * If a CD table has to be present then we need to run with ATS
+                * on even though the RID will fail ATS queries with UR. This is
+                * because we have no idea what the PASID's need.
+                */
+               state.cd_needs_ats = true;
+               arm_smmu_attach_prepare(&state, domain);
+               arm_smmu_make_cdtable_ste(ste, master, state.ats_enabled, s1dss);
+       } else {
+               arm_smmu_attach_prepare(&state, domain);
+       }
        arm_smmu_install_ste_for_dev(master, ste);
        arm_smmu_attach_commit(&state);
        mutex_unlock(&arm_smmu_asid_lock);
@@ -2864,7 +2896,6 @@ static int arm_smmu_attach_dev_ste(struct iommu_domain *domain,
         * descriptor from arm_smmu_share_asid().
         */
        arm_smmu_clear_cd(master, IOMMU_NO_PASID);
-       return 0;
 }
 
 static int arm_smmu_attach_dev_identity(struct iommu_domain *domain,
@@ -2874,7 +2905,8 @@ static int arm_smmu_attach_dev_identity(struct iommu_domain *domain,
        struct arm_smmu_master *master = dev_iommu_priv_get(dev);
 
        arm_smmu_make_bypass_ste(master->smmu, &ste);
-       return arm_smmu_attach_dev_ste(domain, dev, &ste);
+       arm_smmu_attach_dev_ste(domain, dev, &ste, STRTAB_STE_1_S1DSS_BYPASS);
+       return 0;
 }
 
 static const struct iommu_domain_ops arm_smmu_identity_ops = {
@@ -2892,7 +2924,9 @@ static int arm_smmu_attach_dev_blocked(struct iommu_domain *domain,
        struct arm_smmu_ste ste;
 
        arm_smmu_make_abort_ste(&ste);
-       return arm_smmu_attach_dev_ste(domain, dev, &ste);
+       arm_smmu_attach_dev_ste(domain, dev, &ste,
+                               STRTAB_STE_1_S1DSS_TERMINATE);
+       return 0;
 }
 
 static const struct iommu_domain_ops arm_smmu_blocked_ops = {

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index d175d9eee6c61b7d1bccc8f3e2bc643dacdf0594..30459a800c7b2de3f106160425384dfb97f2d33f 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -761,8 +761,8 @@ void arm_smmu_make_abort_ste(struct arm_smmu_ste *target);
 void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu,
                              struct arm_smmu_ste *target);
 void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target,
-                              struct arm_smmu_master *master,
-                              bool ats_enabled);
+                              struct arm_smmu_master *master, bool ats_enabled,
+                              unsigned int s1dss);
 void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target,
                                 struct arm_smmu_master *master,
                                 struct arm_smmu_domain *smmu_domain,