usb: dwc3: core: Set force_gen1 bit for all applicable SuperSpeed ports

Currently if the maximum-speed is set to Super Speed for a 3.1 Gen2
capable controller, the FORCE_GEN1 bit of LLUCTL register is set only
for one SuperSpeed port (or the first port) present. Modify the logic
to set the FORCE_GEN1 bit for all ports if speed is being limited to
Gen-1.

Suggested-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20241112182018.199392-1-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 9b888d33e64df2323eb6df74ff62a7ccdcf7c99e..67aefdbe1d5fc550671879ff5eb0f1c72dcbf21d 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1470,9 +1470,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
        if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
            (DWC3_IP_IS(DWC31)) &&
            dwc->maximum_speed == USB_SPEED_SUPER) {
-               reg = dwc3_readl(dwc->regs, DWC3_LLUCTL);
-               reg |= DWC3_LLUCTL_FORCE_GEN1;
-               dwc3_writel(dwc->regs, DWC3_LLUCTL, reg);
+               int i;
+
+               for (i = 0; i < dwc->num_usb3_ports; i++) {
+                       reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i));
+                       reg |= DWC3_LLUCTL_FORCE_GEN1;
+                       dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg);
+               }
        }
 
        return 0;

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8306b39e5c64d567af2c7b69aca0929889c0e6f7..2dccd8fa7efdd840ca800f4e5228269d9c5e2386 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -179,7 +179,7 @@
 #define DWC3_OEVTEN            0xcc0C
 #define DWC3_OSTS              0xcc10
 
-#define DWC3_LLUCTL            0xd024
+#define DWC3_LLUCTL(n)         (0xd024 + ((n) * 0x80))
 
 /* Bit fields */