drm/amd/display: Fix for hdmi frame pack stereo

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 00961bc37200ccd53e29168bb3c8f673fd20effe..4486121e3986a06ddbb14d0a07ebe7340f8a522e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -987,7 +987,15 @@ bool dcn_validate_bandwidth(
                        if (pipe->surface) {
                                struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
 
-                               if (v->dpp_per_plane[input_idx] == 2) {
+                               if (v->dpp_per_plane[input_idx] == 2 ||
+                                       ((pipe->stream->public.view_format ==
+                                         VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+                                         pipe->stream->public.view_format ==
+                                         VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+                                       (pipe->stream->public.timing.timing_3d_format ==
+                                        TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+                                        pipe->stream->public.timing.timing_3d_format ==
+                                        TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
                                        if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
                                                /* update previously split pipe */
                                                hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a9ddd0756b3be5b1fe18baa0fb9bc97beee8ff2b..1d2e421e8d0a190372b88c4e0fcb4bfdb4295b4d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -967,7 +967,6 @@ bool dc_commit_streams(
                                        DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
 
                        core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
-                       dc_enable_stereo(dc, context, streams, stream_count);
                }
 
                CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}",
@@ -982,7 +981,7 @@ bool dc_commit_streams(
                                context->streams[i]->public.timing.v_total,
                                context->streams[i]->public.timing.pix_clk_khz);
        }
-
+       dc_enable_stereo(dc, context, streams, stream_count);
        dc_resource_validate_ctx_destruct(core_dc->current_context);
        dm_free(core_dc->current_context);
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index fb033b69e2bff59459612df1332cda8f2568787c..ddf032214dc35f451ee7846efd68b8039c1f921a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -626,7 +626,7 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 
        if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
                pipe_ctx->scl_data.ratios.horz.value *= 2;
-       else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
+       else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
                pipe_ctx->scl_data.ratios.vert.value *= 2;
 
        pipe_ctx->scl_data.ratios.vert.value = div64_s64(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cc67707b56d03767e5532e0baffd1321e7d9f360..d38570e6d4d29daa280bff408d9665d69b87245e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -891,7 +891,6 @@ static void reset_hw_ctx_wrap(
        }
 }
 
-
 static bool patch_address_for_sbs_tb_stereo(
                struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 {
@@ -904,11 +903,17 @@ static bool patch_address_for_sbs_tb_stereo(
                 pipe_ctx->stream->public.timing.timing_3d_format ==
                 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
                *addr = surface->public.address.grph_stereo.left_addr;
-               surface->public.address.grph_stereo.left_addr =\
+               surface->public.address.grph_stereo.left_addr =
                surface->public.address.grph_stereo.right_addr;
                return true;
+       } else {
+               if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE &&
+                       surface->public.address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
+                       surface->public.address.type = PLN_ADDR_TYPE_GRPH_STEREO;
+                       surface->public.address.grph_stereo.right_addr =
+                       surface->public.address.grph_stereo.left_addr;
+               }
        }
-
        return false;
 }