PCI: add more checking to ICH region quirks

Per ICH4 and ICH6 specs, ACPI and GPIO regions are valid iff ACPI_EN
and GPIO_EN bits are set to 1. Add checks for these bits into the
quirks prior to the region creation.

While at it, name the constants by macros.

Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Renninger <trenn@suse.de>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ff01bfb3cc29106e3797cf3ca7bdc3e363cfe27a..9e23912c97ac96399ba7e8fffd71dc20fed58279 100644 (file)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -533,6 +533,17 @@ static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_82371AB_3,  quirk_piix4_acpi);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,  PCI_DEVICE_ID_INTEL_82443MX_3,  quirk_piix4_acpi);
 
+#define ICH_PMBASE     0x40
+#define ICH_ACPI_CNTL  0x44
+#define  ICH4_ACPI_EN  0x10
+#define  ICH6_ACPI_EN  0x80
+#define ICH4_GPIOBASE  0x58
+#define ICH4_GPIO_CNTL 0x5c
+#define  ICH4_GPIO_EN  0x10
+#define ICH6_GPIOBASE  0x48
+#define ICH6_GPIO_CNTL 0x4c
+#define  ICH6_GPIO_EN  0x10
+
 /*
  * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
  *     0x40 (128 bytes of ACPI, GPIO & TCO registers)
@@ -541,12 +552,21 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,     PCI_DEVICE_ID_INTEL_82443MX_3,  qui
 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
 {
        u32 region;
+       u8 enable;
 
-       pci_read_config_dword(dev, 0x40, &region);
-       quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
+       pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
+       if (enable & ICH4_ACPI_EN) {
+               pci_read_config_dword(dev, ICH_PMBASE, &region);
+               quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
+                               "ICH4 ACPI/GPIO/TCO");
+       }
 
-       pci_read_config_dword(dev, 0x58, &region);
-       quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
+       pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
+       if (enable & ICH4_GPIO_EN) {
+               pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
+               quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES + 1,
+                               "ICH4 GPIO");
+       }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,                quirk_ich4_lpc_acpi);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,                quirk_ich4_lpc_acpi);
@@ -562,12 +582,21 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,               qui
 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
 {
        u32 region;
+       u8 enable;
 
-       pci_read_config_dword(dev, 0x40, &region);
-       quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
+       pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
+       if (enable & ICH6_ACPI_EN) {
+               pci_read_config_dword(dev, ICH_PMBASE, &region);
+               quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
+                               "ICH6 ACPI/GPIO/TCO");
+       }
 
-       pci_read_config_dword(dev, 0x48, &region);
-       quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
+       pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
+       if (enable & ICH4_GPIO_EN) {
+               pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
+               quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES + 1,
+                               "ICH6 GPIO");
+       }
 }
 
 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)