clk: socfpga: allow compile testing of Stratix 10 / Agilex clocks

The Stratix 10 / Agilex / N5X clocks do not use anything other than OF
or COMMON_CLK so they should be compile testable on most of the
platforms.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 96802294d35ad4a89361f4f0b9cabc20dc0ab72a..9b582b3fca34f2683048cb0fe6cae4ef0148dcd3 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -104,7 +104,7 @@ obj-y                                       += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)            += rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)       += samsung/
 obj-$(CONFIG_CLK_SIFIVE)               += sifive/
-obj-$(CONFIG_ARCH_INTEL_SOCFPGA)       += socfpga/
+obj-y                                  += socfpga/
 obj-$(CONFIG_PLAT_SPEAR)               += spear/
 obj-y                                  += sprd/
 obj-$(CONFIG_ARCH_STI)                 += st/

diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig
index b6c5b97371747d82e070555aafccfbdd634c1908..b62ede8cad01619be482c3a9ef400b5072bd59cc 100644 (file)
--- a/drivers/clk/socfpga/Kconfig
+++ b/drivers/clk/socfpga/Kconfig
@@ -1,6 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0
+config CLK_INTEL_SOCFPGA
+       bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA
+       default ARCH_INTEL_SOCFPGA
+       help
+         Support for the clock controllers present on Intel SoCFPGA and eASIC
+         devices like Stratix 10, Agilex and N5X eASIC.
+
+if CLK_INTEL_SOCFPGA
+
 config CLK_INTEL_SOCFPGA64
-       bool
-       # Intel Stratix / Agilex / N5X clock controller support
+       bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
        default ARM64 && ARCH_INTEL_SOCFPGA
-       depends on ARM64 && ARCH_INTEL_SOCFPGA
+
+endif # CLK_INTEL_SOCFPGA