drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10*

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d3af9bdb6cc244cd972dd106e40c021fea4f9851..06bcccd8eda76fb87c3fb7b0f92ee014d40a319b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5229,10 +5229,10 @@ static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
        uint32_t tmp;
 
        /* enable Save Restore Machine */
-       tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
+       tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
        tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
        tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
-       WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+       WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
 }
 
 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
@@ -7937,12 +7937,12 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 {
        u32 reg, data;
-
+       /* not for *_SOC15 */
        reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
        if (amdgpu_sriov_is_pp_one_vf(adev))
                data = RREG32_NO_KIQ(reg);
        else
-               data = RREG32(reg);
+               data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
 
        data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
        data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
@@ -8684,16 +8684,16 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
 
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
-               cp_int_cntl = RREG32(cp_int_cntl_reg);
+               cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
                                            TIME_STAMP_INT_ENABLE, 0);
-               WREG32(cp_int_cntl_reg, cp_int_cntl);
+               WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
                break;
        case AMDGPU_IRQ_STATE_ENABLE:
-               cp_int_cntl = RREG32(cp_int_cntl_reg);
+               cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
                                            TIME_STAMP_INT_ENABLE, 1);
-               WREG32(cp_int_cntl_reg, cp_int_cntl);
+               WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
                break;
        default:
                break;
@@ -8737,16 +8737,16 @@ static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev
 
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
-               mec_int_cntl = RREG32(mec_int_cntl_reg);
+               mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
                mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
                                             TIME_STAMP_INT_ENABLE, 0);
-               WREG32(mec_int_cntl_reg, mec_int_cntl);
+               WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
                break;
        case AMDGPU_IRQ_STATE_ENABLE:
-               mec_int_cntl = RREG32(mec_int_cntl_reg);
+               mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
                mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
                                             TIME_STAMP_INT_ENABLE, 1);
-               WREG32(mec_int_cntl_reg, mec_int_cntl);
+               WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
                break;
        default:
                break;
@@ -8942,20 +8942,20 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
                                            GENERIC2_INT_ENABLE, 0);
                        WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 
-                       tmp = RREG32(target);
+                       tmp = RREG32_SOC15_IP(GC, target);
                        tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
                                            GENERIC2_INT_ENABLE, 0);
-                       WREG32(target, tmp);
+                       WREG32_SOC15_IP(GC, target, tmp);
                } else {
                        tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
                        tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
                                            GENERIC2_INT_ENABLE, 1);
                        WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 
-                       tmp = RREG32(target);
+                       tmp = RREG32_SOC15_IP(GC, target);
                        tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
                                            GENERIC2_INT_ENABLE, 1);
-                       WREG32(target, tmp);
+                       WREG32_SOC15_IP(GC, target, tmp);
                }
                break;
        default: