[ASPEED_CLK_GATE_RSACLK] =      { 24, -1, "rsaclk-gate",        NULL,   0 }, /* RSA */
        [ASPEED_CLK_GATE_UART3CLK] =    { 25, -1, "uart3clk-gate",      "uart", 0 }, /* UART3 */
        [ASPEED_CLK_GATE_UART4CLK] =    { 26, -1, "uart4clk-gate",      "uart", 0 }, /* UART4 */
-       [ASPEED_CLK_GATE_SDCLKCLK] =    { 27, 16, "sdclk-gate",         NULL,   0 }, /* SDIO/SD */
+       [ASPEED_CLK_GATE_SDCLK] =       { 27, 16, "sdclk-gate",         NULL,   0 }, /* SDIO/SD */
        [ASPEED_CLK_GATE_LHCCLK] =      { 28, -1, "lhclk-gate",         "lhclk", 0 }, /* LPC master/LPC+ */
 };
 
 
 #define ASPEED_CLK_GATE_RSACLK         19
 #define ASPEED_CLK_GATE_UART3CLK       20
 #define ASPEED_CLK_GATE_UART4CLK       21
-#define ASPEED_CLK_GATE_SDCLKCLK       22
+#define ASPEED_CLK_GATE_SDCLK          22
 #define ASPEED_CLK_GATE_LHCCLK         23
 #define ASPEED_CLK_HPLL                        24
 #define ASPEED_CLK_AHB                 25